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https://github.com/c64scene-ar/llvm-6502.git
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44b2b9dc1a
We had stored both f64 values and v2f64, etc. values in the VSX registers. This worked, but was suboptimal because we would always spill 16-byte values even through we almost always had scalar 8-byte values. This resulted in an increase in stack-size use, extra memory bandwidth, etc. To fix this, I've added 64-bit subregisters of the Altivec registers, and combined those with the existing scalar floating-point registers to form a class of VSX scalar floating-point registers. The ABI code has also been enhanced to use this register class and some other necessary improvements have been made. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205075 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.9 KiB
LLVM
50 lines
1.9 KiB
LLVM
; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define double @foo1(double %a) nounwind {
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entry:
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
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br label %return
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; CHECK: @foo1
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; CHECK: xxlor [[R1:[0-9]+]], 1, 1
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; CHECK: xxlor 1, [[R1]], [[R1]]
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; CHECK: blr
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return: ; preds = %entry
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ret double %a
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}
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define double @foo2(double %a) nounwind {
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entry:
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%b = fadd double %a, %a
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
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br label %return
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; CHECK: @foo2
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; CHECK: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
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; CHECK: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
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; CHECK: blr
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return: ; preds = %entry
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ret double %b
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}
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define double @foo3(double %a) nounwind {
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entry:
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
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br label %return
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; CHECK: @foo3
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; CHECK: stxsdx 1,
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; CHECK: lxsdx [[R1:[0-9]+]],
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; CHECK: xsadddp 1, [[R1]], [[R1]]
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; CHECK: blr
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return: ; preds = %entry
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%b = fadd double %a, %a
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ret double %b
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}
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