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cf4525bd20
* Implement memory freeing for instruction temporaries git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1653 91177308-0d34-0410-b5e6-96231b3b80d8
330 lines
10 KiB
C++
330 lines
10 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// Sparc.cpp
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//
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// Purpose:
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//
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// History:
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// 7/15/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "SparcInternals.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/Method.h"
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#include <iostream>
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using std::cerr;
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// Build the MachineInstruction Description Array...
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const MachineInstrDescriptor SparcMachineInstrDesc[] = {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS },
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#include "SparcInstr.def"
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};
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//----------------------------------------------------------------------------
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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//----------------------------------------------------------------------------
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//
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TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
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//----------------------------------------------------------------------------
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// Entry point for register allocation for a module
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//----------------------------------------------------------------------------
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void AllocateRegisters(Method *M, TargetMachine &target)
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{
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if ( (M)->isExternal() ) // don't process prototypes
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return;
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if( DEBUG_RA )
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cerr << "\n******************** Method "<< M->getName()
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<< " ********************\n";
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MethodLiveVarInfo LVI(M ); // Analyze live varaibles
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LVI.analyze();
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PhyRegAlloc PRA(M, target, &LVI); // allocate registers
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PRA.allocateRegisters();
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if( DEBUG_RA ) cerr << "\nRegister allocation complete!\n";
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}
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//---------------------------------------------------------------------------
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// Function InsertPrologCode
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// Function InsertEpilogCode
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// Function InsertPrologEpilog
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//
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// Insert prolog code at the unique method entry point.
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// Insert epilog code at each method exit point.
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// InsertPrologEpilog invokes these only if the method is not compiled
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// with the leaf method optimization.
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//---------------------------------------------------------------------------
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static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
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static void
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InsertPrologCode(Method* method, TargetMachine& target)
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{
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BasicBlock* entryBB = method->getEntryNode();
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unsigned N = GetInstructionsForProlog(entryBB, target, minstrVec);
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assert(N <= MAX_INSTR_PER_VMINSTR);
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if (N > 0)
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{
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MachineCodeForBasicBlock& bbMvec = entryBB->getMachineInstrVec();
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bbMvec.insert(bbMvec.begin(), minstrVec, minstrVec+N);
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}
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}
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static void
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InsertEpilogCode(Method* method, TargetMachine& target)
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{
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for (Method::iterator I=method->begin(), E=method->end(); I != E; ++I)
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if ((*I)->getTerminator()->getOpcode() == Instruction::Ret)
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{
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BasicBlock* exitBB = *I;
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unsigned N = GetInstructionsForEpilog(exitBB, target, minstrVec);
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MachineCodeForBasicBlock& bbMvec = exitBB->getMachineInstrVec();
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MachineCodeForInstruction &termMvec =
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MachineCodeForInstruction::get(exitBB->getTerminator());
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// Remove the NOPs in the delay slots of the return instruction
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const MachineInstrInfo &mii = target.getInstrInfo();
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unsigned numNOPs = 0;
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while (termMvec.back()->getOpCode() == NOP)
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{
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assert( termMvec.back() == bbMvec.back());
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termMvec.pop_back();
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bbMvec.pop_back();
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++numNOPs;
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}
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assert(termMvec.back() == bbMvec.back());
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// Check that we found the right number of NOPs and have the right
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// number of instructions to replace them.
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unsigned ndelays = mii.getNumDelaySlots(termMvec.back()->getOpCode());
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assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
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assert(N == ndelays && "Cannot use epilog code for delay slots?");
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// Append the epilog code to the end of the basic block.
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bbMvec.push_back(minstrVec[0]);
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}
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}
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// Insert SAVE/RESTORE instructions for the method
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static void
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InsertPrologEpilog(Method *method, TargetMachine &target)
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{
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MachineCodeForMethod& mcodeInfo = MachineCodeForMethod::get(method);
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if (mcodeInfo.isCompiledAsLeafMethod())
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return; // nothing to do
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InsertPrologCode(method, target);
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InsertEpilogCode(method, target);
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}
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//---------------------------------------------------------------------------
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// class UltraSparcSchedInfo
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//
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// Purpose:
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// Scheduling information for the UltraSPARC.
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// Primarily just initializes machine-dependent parameters in
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// class MachineSchedInfo.
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//---------------------------------------------------------------------------
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/*ctor*/
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UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt)
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: MachineSchedInfo(tgt,
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(unsigned int) SPARC_NUM_SCHED_CLASSES,
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SparcRUsageDesc,
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SparcInstrUsageDeltas,
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SparcInstrIssueDeltas,
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sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
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sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
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{
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maxNumIssueTotal = 4;
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longestIssueConflict = 0; // computed from issuesGaps[]
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branchMispredictPenalty = 4; // 4 for SPARC IIi
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branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
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l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
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l1ICacheMissPenalty = 8; // ? for SPARC IIi
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inOrderLoads = true; // true for SPARC IIi
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inOrderIssue = true; // true for SPARC IIi
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inOrderExec = false; // false for most architectures
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inOrderRetire= true; // true for most architectures
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// must be called after above parameters are initialized.
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this->initializeResources();
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}
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void
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UltraSparcSchedInfo::initializeResources()
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{
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// Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
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MachineSchedInfo::initializeResources();
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// Machine-dependent fixups go here. None for now.
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}
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//---------------------------------------------------------------------------
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// class UltraSparcFrameInfo
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//
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// Purpose:
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// Interface to stack frame layout info for the UltraSPARC.
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// Starting offsets for each area of the stack frame are aligned at
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// a multiple of getStackFrameSizeAlignment().
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//---------------------------------------------------------------------------
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int
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UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineCodeForMethod& ,
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bool& pos) const
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{
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pos = false; // static stack area grows downwards
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return StaticAreaOffsetFromFP;
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}
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int
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UltraSparcFrameInfo::getRegSpillAreaOffset(MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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pos = false; // static stack area grows downwards
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unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
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if (int mod = autoVarsSize % getStackFrameSizeAlignment())
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autoVarsSize += (getStackFrameSizeAlignment() - mod);
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return StaticAreaOffsetFromFP - autoVarsSize;
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}
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int
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UltraSparcFrameInfo::getTmpAreaOffset(MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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pos = false; // static stack area grows downwards
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unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
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unsigned int spillAreaSize = mcInfo.getRegSpillsSize();
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int offset = autoVarsSize + spillAreaSize;
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if (int mod = offset % getStackFrameSizeAlignment())
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offset += (getStackFrameSizeAlignment() - mod);
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return StaticAreaOffsetFromFP - offset;
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}
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int
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UltraSparcFrameInfo::getDynamicAreaOffset(MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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// dynamic stack area grows downwards starting at top of opt-args area
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unsigned int optArgsSize = mcInfo.getMaxOptionalArgsSize();
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int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP;
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assert(offset % getStackFrameSizeAlignment() == 0);
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return offset;
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}
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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//
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// Purpose:
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// Primary interface to machine description for the UltraSPARC.
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// Primarily just initializes machine-dependent parameters in
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// class TargetMachine, and creates machine-dependent subclasses
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// for classes such as MachineInstrInfo.
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//
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//---------------------------------------------------------------------------
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UltraSparc::UltraSparc()
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: TargetMachine("UltraSparc-Native"),
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instrInfo(*this),
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schedInfo(*this),
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regInfo(*this),
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frameInfo(*this),
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cacheInfo(*this)
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{
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optSizeForSubWordData = 4;
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minMemOpWordSize = 8;
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maxAtomicMemOpWordSize = 8;
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}
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void
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ApplyPeepholeOptimizations(Method *method, TargetMachine &target)
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{
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return;
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// OptimizeLeafProcedures();
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// DeleteFallThroughBranches();
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// RemoveChainedBranches(); // should be folded with previous
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// RemoveRedundantOps(); // operations with %g0, NOP, etc.
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}
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bool
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UltraSparc::compileMethod(Method *method)
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{
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// Construct and initialize the MachineCodeForMethod object for this method.
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MachineCodeForMethod::construct(method, *this);
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if (SelectInstructionsForMethod(method, *this))
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{
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cerr << "Instruction selection failed for method " << method->getName()
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<< "\n\n";
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return true;
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}
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/*
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if (ScheduleInstructionsWithSSA(method, *this))
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{
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cerr << "Instruction scheduling before allocation failed for method "
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<< method->getName() << "\n\n";
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return true;
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}
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*/
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AllocateRegisters(method, *this); // allocate registers
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ApplyPeepholeOptimizations(method, *this); // machine-dependent peephole opts
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InsertPrologEpilog(method, *this);
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return false;
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}
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static void freeMachineCode(Instruction *I) {
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MachineCodeForInstruction::destroy(I);
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}
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//
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// freeCompiledMethod - Release all memory associated with the compiled image
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// for this method.
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//
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void
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UltraSparc::freeCompiledMethod(Method *M)
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{
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for_each(M->inst_begin(), M->inst_end(), freeMachineCode);
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// Don't destruct MachineCodeForMethod - The global printer needs it
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//MachineCodeForMethod::destruct(M);
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}
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