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https://github.com/c64scene-ar/llvm-6502.git
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d950941e13
Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
1.9 KiB
LLVM
81 lines
1.9 KiB
LLVM
; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs > %t
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define fastcc void @Evaluate() {
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entry:
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br i1 false, label %cond_false186, label %cond_true
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cond_true: ; preds = %entry
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ret void
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cond_false186: ; preds = %entry
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br i1 false, label %cond_true293, label %bb203
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bb203: ; preds = %cond_false186
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ret void
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cond_true293: ; preds = %cond_false186
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br i1 false, label %cond_true298, label %cond_next317
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cond_true298: ; preds = %cond_true293
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br i1 false, label %cond_next518, label %cond_true397.preheader
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cond_next317: ; preds = %cond_true293
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ret void
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cond_true397.preheader: ; preds = %cond_true298
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ret void
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cond_next518: ; preds = %cond_true298
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br i1 false, label %bb1069, label %cond_true522
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cond_true522: ; preds = %cond_next518
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ret void
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bb1069: ; preds = %cond_next518
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br i1 false, label %cond_next1131, label %bb1096
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bb1096: ; preds = %bb1069
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ret void
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cond_next1131: ; preds = %bb1069
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br i1 false, label %cond_next1207, label %cond_true1150
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cond_true1150: ; preds = %cond_next1131
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ret void
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cond_next1207: ; preds = %cond_next1131
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br i1 false, label %cond_next1219, label %cond_true1211
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cond_true1211: ; preds = %cond_next1207
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ret void
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cond_next1219: ; preds = %cond_next1207
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br i1 false, label %cond_true1223, label %cond_next1283
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cond_true1223: ; preds = %cond_next1219
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br i1 false, label %cond_true1254, label %cond_true1264
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cond_true1254: ; preds = %cond_true1223
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br i1 false, label %bb1567, label %cond_true1369.preheader
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cond_true1264: ; preds = %cond_true1223
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ret void
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cond_next1283: ; preds = %cond_next1219
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ret void
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cond_true1369.preheader: ; preds = %cond_true1254
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ret void
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bb1567: ; preds = %cond_true1254
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%tmp1605 = load i8* null ; <i8> [#uses=1]
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%tmp1606 = icmp eq i8 %tmp1605, 0 ; <i1> [#uses=1]
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br i1 %tmp1606, label %cond_next1637, label %cond_true1607
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cond_true1607: ; preds = %bb1567
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ret void
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cond_next1637: ; preds = %bb1567
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ret void
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}
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