Moritz Roth 8c4e64af8a [Thumb] Make load/store optimizer less conservative. ... If it's safe to clobber the condition flags, we can do a few extra things: it's then possible to reset the base register writeback using a SUBS, so we can try to merge even if the base register isn't dead after the merged instruction. This is effectively a (heavily bug-fixed) rewrite of r208992. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218386 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-24 16:35:50 +00:00
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AArch64	[FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1).	2014-09-22 21:08:53 +00:00
ARM	Fix swift-atomics testcase	2014-09-23 23:18:01 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	[Power] Use AtomicExpandPass for fence insertion, and use lwsync where appropriate	2014-09-23 20:46:49 +00:00
R600	R600/SI: Fix weird CHECK-DAG usage	2014-09-24 02:14:26 +00:00
SPARC
SystemZ
Thumb	[Thumb] Make load/store optimizer less conservative.	2014-09-24 16:35:50 +00:00
Thumb2
X86	[x86] Teach the instruction lowering to add comments describing constant	2014-09-24 09:39:41 +00:00
XCore