mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2661b411cc
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
835 B
CMake
38 lines
835 B
CMake
set(LLVM_REQUIRES_EH 1)
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set(LLVM_REQUIRES_RTTI 1)
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set(LLVM_LINK_COMPONENTS Support)
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add_tablegen(llvm-tblgen LLVM
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AsmMatcherEmitter.cpp
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AsmWriterEmitter.cpp
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AsmWriterInst.cpp
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CallingConvEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenInstruction.cpp
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CodeGenRegisters.cpp
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CodeGenSchedule.cpp
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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DAGISelMatcherOpt.cpp
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DAGISelMatcher.cpp
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DFAPacketizerEmitter.cpp
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DisassemblerEmitter.cpp
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EDEmitter.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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PseudoLoweringEmitter.cpp
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RegisterInfoEmitter.cpp
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SetTheory.cpp
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SubtargetEmitter.cpp
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TGValueTypes.cpp
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TableGen.cpp
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X86DisassemblerTables.cpp
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X86ModRMFilters.cpp
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X86RecognizableInstr.cpp
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)
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