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This implements the target-independent lowering for the patchpoint intrinsic. Targets have to implement the FastLowerCall hook to support this intrinsic. Related to <rdar://problem/17427052> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212849 91177308-0d34-0410-b5e6-96231b3b80d8
586 lines
22 KiB
C++
586 lines
22 KiB
C++
//===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the FastISel class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FASTISEL_H
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#define LLVM_CODEGEN_FASTISEL_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/IR/CallingConv.h"
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namespace llvm {
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class AllocaInst;
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class Constant;
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class ConstantFP;
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class CallInst;
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class DataLayout;
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class FunctionLoweringInfo;
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class Instruction;
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class IntrinsicInst;
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class LoadInst;
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class MVT;
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class MachineConstantPool;
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class MachineFrameInfo;
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetLibraryInfo;
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class TargetLowering;
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class TargetMachine;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class User;
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class Value;
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/// This is a fast-path instruction selection class that generates poor code and
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/// doesn't support illegal types or non-trivial lowering, but runs quickly.
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class FastISel {
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public:
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struct ArgListEntry {
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Value *Val;
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Type *Ty;
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bool isSExt : 1;
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bool isZExt : 1;
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bool isInReg : 1;
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bool isSRet : 1;
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bool isNest : 1;
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bool isByVal : 1;
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bool isInAlloca : 1;
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bool isReturned : 1;
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uint16_t Alignment;
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ArgListEntry()
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: Val(nullptr), Ty(nullptr), isSExt(false), isZExt(false), isInReg(false),
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isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
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isReturned(false), Alignment(0) { }
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void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
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};
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typedef std::vector<ArgListEntry> ArgListTy;
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struct CallLoweringInfo {
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Type *RetTy;
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bool RetSExt : 1;
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bool RetZExt : 1;
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bool IsVarArg : 1;
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bool IsInReg : 1;
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bool DoesNotReturn : 1;
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bool IsReturnValueUsed : 1;
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// IsTailCall should be modified by implementations of
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// FastLowerCall that perform tail call conversions.
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bool IsTailCall;
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unsigned NumFixedArgs;
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CallingConv::ID CallConv;
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const Value *Callee;
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const char *SymName;
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ArgListTy Args;
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ImmutableCallSite *CS;
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MachineInstr *Call;
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unsigned ResultReg;
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unsigned NumResultRegs;
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SmallVector<Value *, 16> OutVals;
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SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
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SmallVector<unsigned, 16> OutRegs;
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SmallVector<ISD::InputArg, 4> Ins;
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SmallVector<unsigned, 4> InRegs;
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CallLoweringInfo()
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: RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
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IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
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IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
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Callee(nullptr), SymName(nullptr), CS(nullptr), Call(nullptr),
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ResultReg(0), NumResultRegs(0)
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{}
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CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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const Value *Target, ArgListTy &&ArgsList,
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ImmutableCallSite &Call) {
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RetTy = ResultTy;
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Callee = Target;
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IsInReg = Call.paramHasAttr(0, Attribute::InReg);
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DoesNotReturn = Call.doesNotReturn();
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IsVarArg = FuncTy->isVarArg();
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IsReturnValueUsed = !Call.getInstruction()->use_empty();
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RetSExt = Call.paramHasAttr(0, Attribute::SExt);
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RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
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CallConv = Call.getCallingConv();
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NumFixedArgs = FuncTy->getNumParams();
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Args = std::move(ArgsList);
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CS = &Call;
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return *this;
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}
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CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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const char *Target, ArgListTy &&ArgsList,
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ImmutableCallSite &Call,
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unsigned FixedArgs = ~0U) {
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RetTy = ResultTy;
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Callee = Call.getCalledValue();
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SymName = Target;
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IsInReg = Call.paramHasAttr(0, Attribute::InReg);
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DoesNotReturn = Call.doesNotReturn();
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IsVarArg = FuncTy->isVarArg();
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IsReturnValueUsed = !Call.getInstruction()->use_empty();
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RetSExt = Call.paramHasAttr(0, Attribute::SExt);
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RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
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CallConv = Call.getCallingConv();
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NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
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Args = std::move(ArgsList);
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CS = &Call;
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return *this;
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}
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CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
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const Value *Target, ArgListTy &&ArgsList,
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unsigned FixedArgs = ~0U) {
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RetTy = ResultTy;
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Callee = Target;
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CallConv = CC;
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NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
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Args = std::move(ArgsList);
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return *this;
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}
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CallLoweringInfo &setTailCall(bool Value = true) {
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IsTailCall = Value;
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return *this;
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}
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ArgListTy &getArgs() {
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return Args;
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}
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void clearOuts() {
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OutVals.clear();
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OutFlags.clear();
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OutRegs.clear();
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}
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void clearIns() {
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Ins.clear();
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InRegs.clear();
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}
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};
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protected:
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DenseMap<const Value *, unsigned> LocalValueMap;
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FunctionLoweringInfo &FuncInfo;
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MachineFunction *MF;
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MachineRegisterInfo &MRI;
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MachineFrameInfo &MFI;
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MachineConstantPool &MCP;
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DebugLoc DbgLoc;
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const TargetMachine &TM;
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const DataLayout &DL;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const TargetRegisterInfo &TRI;
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const TargetLibraryInfo *LibInfo;
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/// The position of the last instruction for materializing constants for use
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/// in the current block. It resets to EmitStartPt when it makes sense (for
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/// example, it's usually profitable to avoid function calls between the
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/// definition and the use)
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MachineInstr *LastLocalValue;
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/// The top most instruction in the current block that is allowed for emitting
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/// local variables. LastLocalValue resets to EmitStartPt when it makes sense
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/// (for example, on function calls)
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MachineInstr *EmitStartPt;
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public:
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/// Return the position of the last instruction emitted for materializing
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/// constants for use in the current block.
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MachineInstr *getLastLocalValue() { return LastLocalValue; }
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/// Update the position of the last instruction emitted for materializing
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/// constants for use in the current block.
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void setLastLocalValue(MachineInstr *I) {
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EmitStartPt = I;
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LastLocalValue = I;
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}
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/// Set the current block to which generated machine instructions will be
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/// appended, and clear the local CSE map.
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void startNewBlock();
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/// Return current debug location information.
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DebugLoc getCurDebugLoc() const { return DbgLoc; }
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/// Do "fast" instruction selection for function arguments and append machine
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/// instructions to the current block. Return true if it is successful.
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bool LowerArguments();
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/// Do "fast" instruction selection for the given LLVM IR instruction, and
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/// append generated machine instructions to the current block. Return true if
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/// selection was successful.
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bool SelectInstruction(const Instruction *I);
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/// Do "fast" instruction selection for the given LLVM IR operator
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/// (Instruction or ConstantExpr), and append generated machine instructions
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/// to the current block. Return true if selection was successful.
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bool SelectOperator(const User *I, unsigned Opcode);
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/// Create a virtual register and arrange for it to be assigned the value for
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/// the given LLVM value.
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unsigned getRegForValue(const Value *V);
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/// Look up the value to see if its value is already cached in a register. It
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/// may be defined by instructions across blocks or defined locally.
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unsigned lookUpRegForValue(const Value *V);
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/// This is a wrapper around getRegForValue that also takes care of truncating
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/// or sign-extending the given getelementptr index value.
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std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
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/// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note
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/// that we could have a sequence where multiple LLVM IR instructions are
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/// folded into the same machineinstr. For example we could have:
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///
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/// A: x = load i32 *P
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/// B: y = icmp A, 42
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/// C: br y, ...
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///
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/// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"
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/// (and any other folded instructions) because it is between A and C.
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///
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/// If we succeed folding, return true.
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bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
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/// \brief The specified machine instr operand is a vreg, and that vreg is
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/// being provided by the specified load instruction. If possible, try to
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/// fold the load as an operand to the instruction, returning true if
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/// possible.
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///
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/// This method should be implemented by targets.
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virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
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const LoadInst * /*LI*/) {
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return false;
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}
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/// Reset InsertPt to prepare for inserting instructions into the current
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/// block.
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void recomputeInsertPt();
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/// Remove all dead instructions between the I and E.
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void removeDeadCode(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E);
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struct SavePoint {
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MachineBasicBlock::iterator InsertPt;
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DebugLoc DL;
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};
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/// Prepare InsertPt to begin inserting instructions into the local value area
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/// and return the old insert position.
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SavePoint enterLocalValueArea();
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/// Reset InsertPt to the given old insert position.
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void leaveLocalValueArea(SavePoint Old);
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virtual ~FastISel();
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protected:
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explicit FastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo);
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/// This method is called by target-independent code when the normal FastISel
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/// process fails to select an instruction. This gives targets a chance to
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/// emit code for anything that doesn't fit into FastISel's framework. It
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/// returns true if it was successful.
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virtual bool TargetSelectInstruction(const Instruction *I) = 0;
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/// This method is called by target-independent code to do target specific
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/// argument lowering. It returns true if it was successful.
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virtual bool FastLowerArguments();
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/// \brief This method is called by target-independent code to do target
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/// specific call lowering. It returns true if it was successful.
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virtual bool FastLowerCall(CallLoweringInfo &CLI);
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/// \brief This method is called by target-independent code to do target
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/// specific intrinsic lowering. It returns true if it was successful.
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virtual bool FastLowerIntrinsicCall(const IntrinsicInst *II);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type and opcode be emitted.
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virtual unsigned FastEmit_(MVT VT,
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MVT RetVT,
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unsigned Opcode);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register operand be emitted.
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virtual unsigned FastEmit_r(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, bool Op0IsKill);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register operands be emitted.
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virtual unsigned FastEmit_rr(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register and immediate
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/// operands be emitted.
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virtual unsigned FastEmit_ri(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register and floating-point
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/// immediate operands be emitted.
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virtual unsigned FastEmit_rf(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, bool Op0IsKill,
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const ConstantFP *FPImm);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register and immediate
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/// operands be emitted.
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virtual unsigned FastEmit_rri(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm);
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/// \brief This method is a wrapper of FastEmit_ri.
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///
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/// It first tries to emit an instruction with an immediate operand using
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/// FastEmit_ri. If that fails, it materializes the immediate into a register
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/// and try FastEmit_rr instead.
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unsigned FastEmit_ri_(MVT VT,
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unsigned Opcode,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm, MVT ImmType);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and immediate operand be emitted.
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virtual unsigned FastEmit_i(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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uint64_t Imm);
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/// This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and floating-point immediate
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/// operand be emitted.
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virtual unsigned FastEmit_f(MVT VT,
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MVT RetVT,
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unsigned Opcode,
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const ConstantFP *FPImm);
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/// Emit a MachineInstr with no operands and a result register in the given
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/// register class.
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unsigned FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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/// Emit a MachineInstr with one register operand and a result register in the
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/// given register class.
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unsigned FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill);
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/// Emit a MachineInstr with two register operands and a result register in
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/// the given register class.
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unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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/// Emit a MachineInstr with three register operands and a result register in
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/// the given register class.
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unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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unsigned Op2, bool Op2IsKill);
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/// Emit a MachineInstr with a register operand, an immediate, and a result
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/// register in the given register class.
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unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm);
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/// Emit a MachineInstr with one register operand and two immediate operands.
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unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm1, uint64_t Imm2);
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/// Emit a MachineInstr with two register operands and a result register in
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/// the given register class.
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unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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const ConstantFP *FPImm);
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/// Emit a MachineInstr with two register operands, an immediate, and a result
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/// register in the given register class.
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unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm);
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/// Emit a MachineInstr with two register operands, two immediates operands,
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/// and a result register in the given register class.
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unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm1, uint64_t Imm2);
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/// Emit a MachineInstr with a single immediate operand, and a result register
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/// in the given register class.
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unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm);
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/// Emit a MachineInstr with a two immediate operands.
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unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm1, uint64_t Imm2);
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/// Emit a MachineInstr for an extract_subreg from a specified index of a
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/// superregister to a specified type.
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unsigned FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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uint32_t Idx);
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/// Emit MachineInstrs to compute the value of Op with all but the least
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/// significant bit set to zero.
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unsigned FastEmitZExtFromI1(MVT VT,
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unsigned Op0, bool Op0IsKill);
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/// Emit an unconditional branch to the given block, unless it is the
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/// immediate (fall-through) successor, and update the CFG.
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void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
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void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
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unsigned createResultReg(const TargetRegisterClass *RC);
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/// Try to constrain Op so that it is usable by argument OpNum of the provided
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/// MCInstrDesc. If this fails, create a new virtual register in the correct
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/// class and COPY the value there.
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unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
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unsigned OpNum);
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/// Emit a constant in a register using target-specific logic, such as
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/// constant pool loads.
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virtual unsigned TargetMaterializeConstant(const Constant* C) {
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return 0;
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}
|
|
|
|
/// Emit an alloca address in a register using target-specific logic.
|
|
virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
|
|
return 0;
|
|
}
|
|
|
|
virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {
|
|
return 0;
|
|
}
|
|
|
|
/// \brief Check if \c Add is an add that can be safely folded into \c GEP.
|
|
///
|
|
/// \c Add can be folded into \c GEP if:
|
|
/// - \c Add is an add,
|
|
/// - \c Add's size matches \c GEP's,
|
|
/// - \c Add is in the same basic block as \c GEP, and
|
|
/// - \c Add has a constant operand.
|
|
bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
|
|
|
|
/// Test whether the given value has exactly one use.
|
|
bool hasTrivialKill(const Value *V) const;
|
|
|
|
/// \brief Create a machine mem operand from the given instruction.
|
|
MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
|
|
|
|
bool LowerCallTo(const CallInst *CI, const char *SymName, unsigned NumArgs);
|
|
bool LowerCallTo(CallLoweringInfo &CLI);
|
|
|
|
private:
|
|
bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
|
|
|
|
bool SelectFNeg(const User *I);
|
|
|
|
bool SelectGetElementPtr(const User *I);
|
|
|
|
bool SelectStackmap(const CallInst *I);
|
|
bool SelectPatchpoint(const CallInst *I);
|
|
bool LowerCall(const CallInst *I);
|
|
bool SelectCall(const User *Call);
|
|
bool SelectIntrinsicCall(const IntrinsicInst *II);
|
|
|
|
bool SelectBitCast(const User *I);
|
|
|
|
bool SelectCast(const User *I, unsigned Opcode);
|
|
|
|
bool SelectExtractValue(const User *I);
|
|
|
|
bool SelectInsertValue(const User *I);
|
|
|
|
/// \brief Handle PHI nodes in successor blocks.
|
|
///
|
|
/// Emit code to ensure constants are copied into registers when needed.
|
|
/// Remember the virtual registers that need to be added to the Machine PHI
|
|
/// nodes as input. We cannot just directly add them, because expansion might
|
|
/// result in multiple MBB's for one BB. As such, the start of the BB might
|
|
/// correspond to a different MBB than the end.
|
|
bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
|
|
|
|
/// Helper for getRegForVale. This function is called when the value isn't
|
|
/// already available in a register and must be materialized with new
|
|
/// instructions.
|
|
unsigned materializeRegForValue(const Value *V, MVT VT);
|
|
|
|
/// Clears LocalValueMap and moves the area for the new local variables to the
|
|
/// beginning of the block. It helps to avoid spilling cached variables across
|
|
/// heavy instructions like calls.
|
|
void flushLocalValueMap();
|
|
|
|
bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
|
|
const CallInst *CI, unsigned StartIdx);
|
|
bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
|
|
const Value *Callee, bool ForceRetVoidTy,
|
|
CallLoweringInfo &CLI);
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|