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https://github.com/c64scene-ar/llvm-6502.git
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5b17297b3d
Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. This is the 2nd attempt at this after realizing that PassManager::add() may actually delete the pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224059 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
2.8 KiB
C++
91 lines
2.8 KiB
C++
//===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreTargetMachine.h"
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#include "XCoreTargetObjectFile.h"
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#include "XCore.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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/// XCoreTargetMachine ctor - Create an ILP32 architecture model
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///
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XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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TLOF(make_unique<XCoreTargetObjectFile>()),
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Subtarget(TT, CPU, FS, *this) {
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initAsmInfo();
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}
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XCoreTargetMachine::~XCoreTargetMachine() {}
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namespace {
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/// XCore Code Generator Pass Configuration Options.
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class XCorePassConfig : public TargetPassConfig {
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public:
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XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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XCoreTargetMachine &getXCoreTargetMachine() const {
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return getTM<XCoreTargetMachine>();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new XCorePassConfig(this, PM);
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}
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void XCorePassConfig::addIRPasses() {
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addPass(createAtomicExpandPass(&getXCoreTargetMachine()));
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TargetPassConfig::addIRPasses();
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}
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bool XCorePassConfig::addPreISel() {
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addPass(createXCoreLowerThreadLocalPass());
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return false;
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}
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bool XCorePassConfig::addInstSelector() {
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addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
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return false;
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}
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void XCorePassConfig::addPreEmitPass() {
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addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeXCoreTarget() {
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RegisterTargetMachine<XCoreTargetMachine> X(TheXCoreTarget);
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}
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void XCoreTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our XCore pass. This
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// allows the XCore pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createXCoreTargetTransformInfoPass(this));
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}
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