mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
d258eb3ec5
into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166613 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
1.1 KiB
LLVM
61 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=arm | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK: f1:
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; CHECK: subs r
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; CHECK: sbc r
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entry:
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK: f2:
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; CHECK: adc r
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; CHECK: subs r
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; CHECK: sbc r
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entry:
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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; add with live carry
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define i64 @f3(i32 %al, i32 %bl) {
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; CHECK: f3:
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; CHECK: adds r
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; CHECK: adc r
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entry:
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; unsigned wide add
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%aw = zext i32 %al to i64
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%bw = zext i32 %bl to i64
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%cw = add i64 %aw, %bw
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; ch == carry bit
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%ch = lshr i64 %cw, 32
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%dw = add i64 %ch, %bw
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ret i64 %dw
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}
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; rdar://10073745
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define i64 @f4(i64 %x) nounwind readnone {
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entry:
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; CHECK: f4:
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; CHECK: rsbs r
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; CHECK: rsc r
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%0 = sub nsw i64 0, %x
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ret i64 %0
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}
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; rdar://12559385
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define i64 @f5(i32 %vi) {
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entry:
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; CHECK: f5:
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; CHECK: movw [[REG:r[0-9]+]], #36102
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; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
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%v0 = zext i32 %vi to i64
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%v1 = xor i64 %v0, -155057456198619
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%v4 = add i64 %v1, 155057456198619
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%v5 = add i64 %v4, %v1
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ret i64 %v5
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}
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