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https://github.com/c64scene-ar/llvm-6502.git
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23125d02d9
This commit allows the ARM integrated assembler to parse and assemble the code with .eabi_attribute, .cpu, and .fpu directives. To implement the feature, this commit moves the code from AttrEmitter to ARMTargetStreamers, and several new test cases related to cortex-m4, cortex-r5, and cortex-a15 are added. Besides, this commit also change the Subtarget->isFPOnlySP() to Subtarget->hasD16() to match the usage of .fpu directive. This commit changes the test cases: * Several .eabi_attribute directives in 2010-09-29-mc-asm-header-test.ll are removed because the .fpu directive already cover the functionality. * In the Cortex-A15 test case, the value for Tag_Advanced_SIMD_arch has be changed from 1 to 2, which is more precise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
720 B
ArmAsm
27 lines
720 B
ArmAsm
@ Check multiple .fpu directives.
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@ The later .fpu directive should overwrite the earlier one.
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@ See also: directive-fpu-multiple2.s.
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@ RUN: llvm-mc < %s -triple arm-unknown-linux-gnueabi -filetype=obj \
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@ RUN: | llvm-readobj -s -sd | FileCheck %s
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.fpu neon
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.fpu vfpv4
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@ CHECK: Name: .ARM.attributes
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@ CHECK-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
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@ CHECK-NEXT: Flags [ (0x0)
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@ CHECK-NEXT: ]
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@ CHECK-NEXT: Address: 0x0
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@ CHECK-NEXT: Offset: 0x34
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@ CHECK-NEXT: Size: 18
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@ CHECK-NEXT: Link: 0
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@ CHECK-NEXT: Info: 0
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@ CHECK-NEXT: AddressAlignment: 1
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@ CHECK-NEXT: EntrySize: 0
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@ CHECK-NEXT: SectionData (
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@ CHECK-NEXT: 0000: 41110000 00616561 62690001 07000000
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@ CHECK-NEXT: 0010: 0A05
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@ CHECK-NEXT: )
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