mirror of
https://github.com/c64scene-ar/llvm-6502.git
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82509e5c62
1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
301 lines
12 KiB
TableGen
301 lines
12 KiB
TableGen
//===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM v6 processors.
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//
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//===----------------------------------------------------------------------===//
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// Model based on ARM1176
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//
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// Functional Units
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def V6_Pipe : FuncUnit; // pipeline
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// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual"
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//
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def ARMV6Itineraries : ProcessorItineraries<
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[V6_Pipe], [], [
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//
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// No operand cycles
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InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
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//
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// Binary Instructions that produce a result
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InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
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InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
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InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
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//
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// Bitwise Instructions that produce a result
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InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
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InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
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InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
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//
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// Unary Instructions that produce a result
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InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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//
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// Zero and sign extension instructions
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InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>,
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InstrItinData<IIC_iEXTAr , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
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InstrItinData<IIC_iEXTAsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
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//
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// Compare instructions
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InstrItinData<IIC_iCMPi , [InstrStage<1, [V6_Pipe]>], [2]>,
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InstrItinData<IIC_iCMPr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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InstrItinData<IIC_iCMPsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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InstrItinData<IIC_iCMPsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
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//
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// Test instructions
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InstrItinData<IIC_iTSTi , [InstrStage<1, [V6_Pipe]>], [2]>,
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InstrItinData<IIC_iTSTr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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InstrItinData<IIC_iTSTsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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InstrItinData<IIC_iTSTsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
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//
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// Move instructions, unconditional
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InstrItinData<IIC_iMOVi , [InstrStage<1, [V6_Pipe]>], [2]>,
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InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
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InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>], [2]>,
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InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>], [3]>,
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InstrItinData<IIC_iMOVix2ld , [InstrStage<1, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>], [5]>,
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//
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// Move instructions, conditional
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InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>,
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InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>,
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InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>,
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InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,
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InstrItinData<IIC_iCMOVix2 , [InstrStage<1, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>], [4]>,
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//
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// MVN instructions
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InstrItinData<IIC_iMVNi , [InstrStage<1, [V6_Pipe]>], [2]>,
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InstrItinData<IIC_iMVNr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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InstrItinData<IIC_iMVNsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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InstrItinData<IIC_iMVNsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
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// Integer multiply pipeline
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//
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InstrItinData<IIC_iMUL16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,
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InstrItinData<IIC_iMAC16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1, 2]>,
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InstrItinData<IIC_iMUL32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1]>,
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InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>,
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InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>,
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InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>,
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// Integer load pipeline
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//
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// Immediate offset
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InstrItinData<IIC_iLoad_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>,
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InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [V6_Pipe]>], [4, 1]>,
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InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>,
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//
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// Register offset
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InstrItinData<IIC_iLoad_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,
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InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,
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InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,
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//
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// Scaled register offset, issues over 2 cycles
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InstrItinData<IIC_iLoad_si , [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>,
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InstrItinData<IIC_iLoad_bh_si, [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>,
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//
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// Immediate offset with update
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InstrItinData<IIC_iLoad_iu , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,
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InstrItinData<IIC_iLoad_bh_iu, [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,
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//
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// Register offset with update
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InstrItinData<IIC_iLoad_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>,
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InstrItinData<IIC_iLoad_bh_ru, [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>,
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InstrItinData<IIC_iLoad_d_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>,
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//
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// Scaled register offset with update, issues over 2 cycles
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InstrItinData<IIC_iLoad_siu, [InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>,
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InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>,
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//
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// Load multiple, def is the 5th operand.
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InstrItinData<IIC_iLoad_m , [InstrStage<3, [V6_Pipe]>], [1, 1, 1, 1, 4]>,
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//
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// Load multiple + update, defs are the 1st and 5th operands.
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InstrItinData<IIC_iLoad_mu , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 1, 4]>,
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//
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// Load multiple plus branch
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InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>], [1, 2, 1, 1, 4]>,
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//
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// iLoadi + iALUr for t2LDRpci_pic.
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InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>], [3, 1]>,
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//
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// Pop, def is the 3rd operand.
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InstrItinData<IIC_iPop , [InstrStage<3, [V6_Pipe]>], [1, 1, 4]>,
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//
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// Pop + branch, def is the 3rd operand.
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InstrItinData<IIC_iPop_Br, [InstrStage<3, [V6_Pipe]>,
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InstrStage<1, [V6_Pipe]>], [1, 2, 4]>,
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// Integer store pipeline
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//
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// Immediate offset
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InstrItinData<IIC_iStore_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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InstrItinData<IIC_iStore_bh_i, [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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InstrItinData<IIC_iStore_d_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
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//
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// Register offset
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InstrItinData<IIC_iStore_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>,
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InstrItinData<IIC_iStore_bh_r, [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>,
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InstrItinData<IIC_iStore_d_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>,
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//
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// Scaled register offset, issues over 2 cycles
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InstrItinData<IIC_iStore_si , [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>,
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InstrItinData<IIC_iStore_bh_si, [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>,
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//
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// Immediate offset with update
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InstrItinData<IIC_iStore_iu , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
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InstrItinData<IIC_iStore_bh_iu, [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
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//
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// Register offset with update
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InstrItinData<IIC_iStore_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>,
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InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>,
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InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>,
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//
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// Scaled register offset with update, issues over 2 cycles
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InstrItinData<IIC_iStore_siu, [InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>,
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InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>,
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//
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// Store multiple
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InstrItinData<IIC_iStore_m , [InstrStage<3, [V6_Pipe]>]>,
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//
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// Store multiple + update
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InstrItinData<IIC_iStore_mu , [InstrStage<3, [V6_Pipe]>], [2]>,
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// Branch
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//
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// no delay slots, so the latency of a branch is unimportant
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InstrItinData<IIC_Br , [InstrStage<1, [V6_Pipe]>]>,
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// VFP
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// Issue through integer pipeline, and execute in NEON unit. We assume
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// RunFast mode so that NFP pipeline is used for single-precision when
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// possible.
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//
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// FP Special Register to Integer Register File Move
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InstrItinData<IIC_fpSTAT , [InstrStage<1, [V6_Pipe]>], [3]>,
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//
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// Single-precision FP Unary
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InstrItinData<IIC_fpUNA32 , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
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//
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// Double-precision FP Unary
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InstrItinData<IIC_fpUNA64 , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
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//
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// Single-precision FP Compare
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InstrItinData<IIC_fpCMP32 , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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//
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// Double-precision FP Compare
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InstrItinData<IIC_fpCMP64 , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
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//
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// Single to Double FP Convert
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InstrItinData<IIC_fpCVTSD , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
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//
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// Double to Single FP Convert
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InstrItinData<IIC_fpCVTDS , [InstrStage<1, [V6_Pipe]>], [5, 2]>,
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//
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// Single-Precision FP to Integer Convert
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InstrItinData<IIC_fpCVTSI , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
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//
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// Double-Precision FP to Integer Convert
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InstrItinData<IIC_fpCVTDI , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
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//
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// Integer to Single-Precision FP Convert
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InstrItinData<IIC_fpCVTIS , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
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//
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// Integer to Double-Precision FP Convert
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InstrItinData<IIC_fpCVTID , [InstrStage<1, [V6_Pipe]>], [9, 2]>,
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//
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// Single-precision FP ALU
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InstrItinData<IIC_fpALU32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,
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//
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// Double-precision FP ALU
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InstrItinData<IIC_fpALU64 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,
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//
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// Single-precision FP Multiply
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InstrItinData<IIC_fpMUL32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,
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//
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// Double-precision FP Multiply
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InstrItinData<IIC_fpMUL64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2]>,
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//
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// Single-precision FP MAC
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InstrItinData<IIC_fpMAC32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>,
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//
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// Double-precision FP MAC
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InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,
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//
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// Single-precision Fused FP MAC
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InstrItinData<IIC_fpFMAC32, [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>,
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//
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// Double-precision Fused FP MAC
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InstrItinData<IIC_fpFMAC64, [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,
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//
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// Single-precision FP DIV
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InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,
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//
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// Double-precision FP DIV
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InstrItinData<IIC_fpDIV64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,
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//
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// Single-precision FP SQRT
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InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,
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//
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// Double-precision FP SQRT
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InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,
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//
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// Integer to Single-precision Move
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InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
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//
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// Integer to Double-precision Move
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InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>,
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//
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// Single-precision to Integer Move
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InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
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//
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// Double-precision to Integer Move
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InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>,
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//
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// Single-precision FP Load
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InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,
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//
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// Double-precision FP Load
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InstrItinData<IIC_fpLoad64 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,
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//
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// FP Load Multiple
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InstrItinData<IIC_fpLoad_m , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 5]>,
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//
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// FP Load Multiple + update
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InstrItinData<IIC_fpLoad_mu, [InstrStage<3, [V6_Pipe]>], [3, 2, 1, 1, 5]>,
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//
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// Single-precision FP Store
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InstrItinData<IIC_fpStore32 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
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//
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// Double-precision FP Store
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpStore64 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
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//
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// FP Store Multiple
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InstrItinData<IIC_fpStore_m, [InstrStage<3, [V6_Pipe]>], [2, 2, 2, 2]>,
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//
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// FP Store Multiple + update
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InstrItinData<IIC_fpStore_mu,[InstrStage<3, [V6_Pipe]>], [3, 2, 2, 2, 2]>
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]>;
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