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7941350101
When trying to rematerialize a value before an instruction that has an early-clobber redefine of the virtual register, make sure to look up the correct value number. Early-clobber defs are moved one slot back, so getBaseIndex is needed to find the used value number. Bugpoint was unable to reduce the test case for this, see PR10388. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135378 91177308-0d34-0410-b5e6-96231b3b80d8
1059 lines
37 KiB
C++
1059 lines
37 KiB
C++
//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The inline spiller modifies the machine function directly instead of
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// inserting spills and restores in VirtRegMap.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "Spiller.h"
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#include "LiveRangeEdit.h"
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#include "VirtRegMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
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STATISTIC(NumSnippets, "Number of snippets included in spills");
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STATISTIC(NumSpills, "Number of spills inserted");
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STATISTIC(NumReloads, "Number of reloads inserted");
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STATISTIC(NumFolded, "Number of folded stack accesses");
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STATISTIC(NumFoldedLoads, "Number of folded loads");
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STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
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STATISTIC(NumOmitReloadSpill, "Number of omitted spills after reloads");
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STATISTIC(NumHoistLocal, "Number of locally hoisted spills");
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STATISTIC(NumHoistGlobal, "Number of globally hoisted spills");
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STATISTIC(NumRedundantSpills, "Number of redundant spills identified");
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namespace {
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class InlineSpiller : public Spiller {
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MachineFunctionPass &Pass;
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MachineFunction &MF;
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LiveIntervals &LIS;
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LiveStacks &LSS;
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AliasAnalysis *AA;
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MachineDominatorTree &MDT;
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MachineLoopInfo &Loops;
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VirtRegMap &VRM;
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MachineFrameInfo &MFI;
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MachineRegisterInfo &MRI;
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const TargetInstrInfo &TII;
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const TargetRegisterInfo &TRI;
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// Variables that are valid during spill(), but used by multiple methods.
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LiveRangeEdit *Edit;
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LiveInterval *StackInt;
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int StackSlot;
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unsigned Original;
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// All registers to spill to StackSlot, including the main register.
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SmallVector<unsigned, 8> RegsToSpill;
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// All COPY instructions to/from snippets.
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// They are ignored since both operands refer to the same stack slot.
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SmallPtrSet<MachineInstr*, 8> SnippetCopies;
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// Values that failed to remat at some point.
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SmallPtrSet<VNInfo*, 8> UsedValues;
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// Information about a value that was defined by a copy from a sibling
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// register.
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struct SibValueInfo {
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// True when all reaching defs were reloads: No spill is necessary.
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bool AllDefsAreReloads;
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// The preferred register to spill.
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unsigned SpillReg;
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// The value of SpillReg that should be spilled.
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VNInfo *SpillVNI;
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// A defining instruction that is not a sibling copy or a reload, or NULL.
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// This can be used as a template for rematerialization.
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MachineInstr *DefMI;
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SibValueInfo(unsigned Reg, VNInfo *VNI)
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: AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}
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};
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// Values in RegsToSpill defined by sibling copies.
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typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
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SibValueMap SibValues;
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// Dead defs generated during spilling.
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SmallVector<MachineInstr*, 8> DeadDefs;
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~InlineSpiller() {}
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public:
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InlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm)
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: Pass(pass),
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MF(mf),
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LIS(pass.getAnalysis<LiveIntervals>()),
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LSS(pass.getAnalysis<LiveStacks>()),
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AA(&pass.getAnalysis<AliasAnalysis>()),
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MDT(pass.getAnalysis<MachineDominatorTree>()),
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Loops(pass.getAnalysis<MachineLoopInfo>()),
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VRM(vrm),
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MFI(*mf.getFrameInfo()),
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MRI(mf.getRegInfo()),
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TII(*mf.getTarget().getInstrInfo()),
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TRI(*mf.getTarget().getRegisterInfo()) {}
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void spill(LiveRangeEdit &);
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private:
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bool isSnippet(const LiveInterval &SnipLI);
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void collectRegsToSpill();
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bool isRegToSpill(unsigned Reg) {
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return std::find(RegsToSpill.begin(),
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RegsToSpill.end(), Reg) != RegsToSpill.end();
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}
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bool isSibling(unsigned Reg);
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MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
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void analyzeSiblingValues();
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bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
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void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
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void markValueUsed(LiveInterval*, VNInfo*);
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bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
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void reMaterializeAll();
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bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
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bool foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr *LoadMI = 0);
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void insertReload(LiveInterval &NewLI, SlotIndex,
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MachineBasicBlock::iterator MI);
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void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
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SlotIndex, MachineBasicBlock::iterator MI);
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void spillAroundUses(unsigned Reg);
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void spillAll();
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};
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}
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namespace llvm {
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Spiller *createInlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm) {
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return new InlineSpiller(pass, mf, vrm);
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}
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}
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//===----------------------------------------------------------------------===//
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// Snippets
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//===----------------------------------------------------------------------===//
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// When spilling a virtual register, we also spill any snippets it is connected
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// to. The snippets are small live ranges that only have a single real use,
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// leftovers from live range splitting. Spilling them enables memory operand
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// folding or tightens the live range around the single use.
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//
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// This minimizes register pressure and maximizes the store-to-load distance for
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// spill slots which can be important in tight loops.
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/// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
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/// otherwise return 0.
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static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
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if (!MI->isFullCopy())
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return 0;
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if (MI->getOperand(0).getReg() == Reg)
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return MI->getOperand(1).getReg();
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if (MI->getOperand(1).getReg() == Reg)
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return MI->getOperand(0).getReg();
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return 0;
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}
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/// isSnippet - Identify if a live interval is a snippet that should be spilled.
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/// It is assumed that SnipLI is a virtual register with the same original as
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/// Edit->getReg().
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bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
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unsigned Reg = Edit->getReg();
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// A snippet is a tiny live range with only a single instruction using it
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// besides copies to/from Reg or spills/fills. We accept:
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//
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// %snip = COPY %Reg / FILL fi#
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// %snip = USE %snip
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// %Reg = COPY %snip / SPILL %snip, fi#
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//
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if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
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return false;
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MachineInstr *UseMI = 0;
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// Check that all uses satisfy our criteria.
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for (MachineRegisterInfo::reg_nodbg_iterator
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RI = MRI.reg_nodbg_begin(SnipLI.reg);
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MachineInstr *MI = RI.skipInstruction();) {
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// Allow copies to/from Reg.
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if (isFullCopyOf(MI, Reg))
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continue;
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// Allow stack slot loads.
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int FI;
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if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
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continue;
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// Allow stack slot stores.
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if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
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continue;
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// Allow a single additional instruction.
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if (UseMI && MI != UseMI)
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return false;
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UseMI = MI;
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}
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return true;
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}
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/// collectRegsToSpill - Collect live range snippets that only have a single
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/// real use.
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void InlineSpiller::collectRegsToSpill() {
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unsigned Reg = Edit->getReg();
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// Main register always spills.
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RegsToSpill.assign(1, Reg);
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SnippetCopies.clear();
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// Snippets all have the same original, so there can't be any for an original
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// register.
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if (Original == Reg)
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return;
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for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
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MachineInstr *MI = RI.skipInstruction();) {
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unsigned SnipReg = isFullCopyOf(MI, Reg);
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if (!isSibling(SnipReg))
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continue;
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LiveInterval &SnipLI = LIS.getInterval(SnipReg);
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if (!isSnippet(SnipLI))
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continue;
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SnippetCopies.insert(MI);
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if (isRegToSpill(SnipReg))
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continue;
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RegsToSpill.push_back(SnipReg);
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DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
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++NumSnippets;
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}
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}
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//===----------------------------------------------------------------------===//
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// Sibling Values
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//===----------------------------------------------------------------------===//
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// After live range splitting, some values to be spilled may be defined by
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// copies from sibling registers. We trace the sibling copies back to the
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// original value if it still exists. We need it for rematerialization.
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//
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// Even when the value can't be rematerialized, we still want to determine if
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// the value has already been spilled, or we may want to hoist the spill from a
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// loop.
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bool InlineSpiller::isSibling(unsigned Reg) {
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return TargetRegisterInfo::isVirtualRegister(Reg) &&
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VRM.getOriginal(Reg) == Original;
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}
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/// traceSiblingValue - Trace a value that is about to be spilled back to the
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/// real defining instructions by looking through sibling copies. Always stay
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/// within the range of OrigVNI so the registers are known to carry the same
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/// value.
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///
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/// Determine if the value is defined by all reloads, so spilling isn't
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/// necessary - the value is already in the stack slot.
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///
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/// Return a defining instruction that may be a candidate for rematerialization.
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///
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MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
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VNInfo *OrigVNI) {
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DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
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<< UseVNI->id << '@' << UseVNI->def << '\n');
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SmallPtrSet<VNInfo*, 8> Visited;
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SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
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WorkList.push_back(std::make_pair(UseReg, UseVNI));
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// Best spill candidate seen so far. This must dominate UseVNI.
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SibValueInfo SVI(UseReg, UseVNI);
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MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def);
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MachineBasicBlock *SpillMBB = UseMBB;
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unsigned SpillDepth = Loops.getLoopDepth(SpillMBB);
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bool SeenOrigPHI = false; // Original PHI met.
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do {
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unsigned Reg;
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VNInfo *VNI;
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tie(Reg, VNI) = WorkList.pop_back_val();
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if (!Visited.insert(VNI))
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continue;
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// Is this value a better spill candidate?
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if (!isRegToSpill(Reg)) {
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MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
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if (MBB == SpillMBB) {
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// This is an alternative def earlier in the same MBB.
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// Hoist the spill as far as possible in SpillMBB. This can ease
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// register pressure:
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//
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// x = def
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// y = use x
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// s = copy x
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//
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// Hoisting the spill of s to immediately after the def removes the
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// interference between x and y:
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//
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// x = def
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// spill x
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// y = use x<kill>
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//
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if (VNI->def < SVI.SpillVNI->def) {
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DEBUG(dbgs() << " hoist in BB#" << MBB->getNumber() << ": "
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<< PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
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<< '\n');
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SVI.SpillReg = Reg;
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SVI.SpillVNI = VNI;
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}
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} else if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
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// This is a valid spill location dominating UseVNI.
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// Prefer to spill at a smaller loop depth.
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unsigned Depth = Loops.getLoopDepth(MBB);
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if (Depth < SpillDepth) {
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DEBUG(dbgs() << " spill depth " << Depth << ": " << PrintReg(Reg)
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<< ':' << VNI->id << '@' << VNI->def << '\n');
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SVI.SpillReg = Reg;
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SVI.SpillVNI = VNI;
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SpillMBB = MBB;
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SpillDepth = Depth;
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}
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}
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}
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// Trace through PHI-defs created by live range splitting.
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if (VNI->isPHIDef()) {
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if (VNI->def == OrigVNI->def) {
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DEBUG(dbgs() << " orig phi value " << PrintReg(Reg) << ':'
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<< VNI->id << '@' << VNI->def << '\n');
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SeenOrigPHI = true;
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continue;
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}
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// Get values live-out of predecessors.
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LiveInterval &LI = LIS.getInterval(Reg);
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MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
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for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
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PE = MBB->pred_end(); PI != PE; ++PI) {
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VNInfo *PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
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if (PVNI)
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WorkList.push_back(std::make_pair(Reg, PVNI));
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}
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continue;
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}
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MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
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assert(MI && "Missing def");
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// Trace through sibling copies.
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if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
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if (isSibling(SrcReg)) {
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LiveInterval &SrcLI = LIS.getInterval(SrcReg);
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VNInfo *SrcVNI = SrcLI.getVNInfoAt(VNI->def.getUseIndex());
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assert(SrcVNI && "Copy from non-existing value");
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DEBUG(dbgs() << " copy of " << PrintReg(SrcReg) << ':'
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<< SrcVNI->id << '@' << SrcVNI->def << '\n');
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WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
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continue;
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}
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}
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// Track reachable reloads.
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int FI;
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if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
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DEBUG(dbgs() << " reload " << PrintReg(Reg) << ':'
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<< VNI->id << "@" << VNI->def << '\n');
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SVI.AllDefsAreReloads = true;
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continue;
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}
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// We have an 'original' def. Don't record trivial cases.
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if (VNI == UseVNI) {
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DEBUG(dbgs() << "Not a sibling copy.\n");
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return MI;
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}
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// Potential remat candidate.
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DEBUG(dbgs() << " def " << PrintReg(Reg) << ':'
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<< VNI->id << '@' << VNI->def << '\t' << *MI);
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SVI.DefMI = MI;
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} while (!WorkList.empty());
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if (SeenOrigPHI || SVI.DefMI)
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SVI.AllDefsAreReloads = false;
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DEBUG({
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if (SVI.AllDefsAreReloads)
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dbgs() << "All defs are reloads.\n";
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else
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dbgs() << "Prefer to spill " << PrintReg(SVI.SpillReg) << ':'
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<< SVI.SpillVNI->id << '@' << SVI.SpillVNI->def << '\n';
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});
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SibValues.insert(std::make_pair(UseVNI, SVI));
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return SVI.DefMI;
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}
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/// analyzeSiblingValues - Trace values defined by sibling copies back to
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/// something that isn't a sibling copy.
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///
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/// Keep track of values that may be rematerializable.
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void InlineSpiller::analyzeSiblingValues() {
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SibValues.clear();
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// No siblings at all?
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if (Edit->getReg() == Original)
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return;
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LiveInterval &OrigLI = LIS.getInterval(Original);
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
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unsigned Reg = RegsToSpill[i];
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LiveInterval &LI = LIS.getInterval(Reg);
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for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
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VE = LI.vni_end(); VI != VE; ++VI) {
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VNInfo *VNI = *VI;
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if (VNI->isUnused())
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continue;
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MachineInstr *DefMI = 0;
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// Check possible sibling copies.
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if (VNI->isPHIDef() || VNI->getCopy()) {
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VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
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assert(OrigVNI && "Def outside original live range");
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if (OrigVNI->def != VNI->def)
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DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
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}
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if (!DefMI && !VNI->isPHIDef())
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DefMI = LIS.getInstructionFromIndex(VNI->def);
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if (DefMI && Edit->checkRematerializable(VNI, DefMI, TII, AA)) {
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DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
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<< VNI->def << " may remat from " << *DefMI);
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}
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}
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}
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}
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/// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
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/// a spill at a better location.
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bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
|
|
SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
|
|
VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getDefIndex());
|
|
assert(VNI && VNI->def == Idx.getDefIndex() && "Not defined by copy");
|
|
SibValueMap::iterator I = SibValues.find(VNI);
|
|
if (I == SibValues.end())
|
|
return false;
|
|
|
|
const SibValueInfo &SVI = I->second;
|
|
|
|
// Let the normal folding code deal with the boring case.
|
|
if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
|
|
return false;
|
|
|
|
// SpillReg may have been deleted by remat and DCE.
|
|
if (!LIS.hasInterval(SVI.SpillReg)) {
|
|
DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
|
|
SibValues.erase(I);
|
|
return false;
|
|
}
|
|
|
|
LiveInterval &SibLI = LIS.getInterval(SVI.SpillReg);
|
|
if (!SibLI.containsValue(SVI.SpillVNI)) {
|
|
DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
|
|
SibValues.erase(I);
|
|
return false;
|
|
}
|
|
|
|
// Conservatively extend the stack slot range to the range of the original
|
|
// value. We may be able to do better with stack slot coloring by being more
|
|
// careful here.
|
|
assert(StackInt && "No stack slot assigned yet.");
|
|
LiveInterval &OrigLI = LIS.getInterval(Original);
|
|
VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
|
|
StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
|
|
DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
|
|
<< *StackInt << '\n');
|
|
|
|
// Already spilled everywhere.
|
|
if (SVI.AllDefsAreReloads) {
|
|
++NumOmitReloadSpill;
|
|
return true;
|
|
}
|
|
// We are going to spill SVI.SpillVNI immediately after its def, so clear out
|
|
// any later spills of the same value.
|
|
eliminateRedundantSpills(SibLI, SVI.SpillVNI);
|
|
|
|
MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
|
|
MachineBasicBlock::iterator MII;
|
|
if (SVI.SpillVNI->isPHIDef())
|
|
MII = MBB->SkipPHIsAndLabels(MBB->begin());
|
|
else {
|
|
MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
|
|
assert(DefMI && "Defining instruction disappeared");
|
|
MII = DefMI;
|
|
++MII;
|
|
}
|
|
// Insert spill without kill flag immediately after def.
|
|
TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
|
|
MRI.getRegClass(SVI.SpillReg), &TRI);
|
|
--MII; // Point to store instruction.
|
|
LIS.InsertMachineInstrInMaps(MII);
|
|
VRM.addSpillSlotUse(StackSlot, MII);
|
|
DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
|
|
|
|
if (MBB == CopyMI->getParent())
|
|
++NumHoistLocal;
|
|
else
|
|
++NumHoistGlobal;
|
|
return true;
|
|
}
|
|
|
|
/// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
|
|
/// redundant spills of this value in SLI.reg and sibling copies.
|
|
void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
|
|
assert(VNI && "Missing value");
|
|
SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
|
|
WorkList.push_back(std::make_pair(&SLI, VNI));
|
|
assert(StackInt && "No stack slot assigned yet.");
|
|
|
|
do {
|
|
LiveInterval *LI;
|
|
tie(LI, VNI) = WorkList.pop_back_val();
|
|
unsigned Reg = LI->reg;
|
|
DEBUG(dbgs() << "Checking redundant spills for "
|
|
<< VNI->id << '@' << VNI->def << " in " << *LI << '\n');
|
|
|
|
// Regs to spill are taken care of.
|
|
if (isRegToSpill(Reg))
|
|
continue;
|
|
|
|
// Add all of VNI's live range to StackInt.
|
|
StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
|
|
DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
|
|
|
|
// Find all spills and copies of VNI.
|
|
for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
|
|
MachineInstr *MI = UI.skipInstruction();) {
|
|
if (!MI->isCopy() && !MI->getDesc().mayStore())
|
|
continue;
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI);
|
|
if (LI->getVNInfoAt(Idx) != VNI)
|
|
continue;
|
|
|
|
// Follow sibling copies down the dominator tree.
|
|
if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
|
|
if (isSibling(DstReg)) {
|
|
LiveInterval &DstLI = LIS.getInterval(DstReg);
|
|
VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getDefIndex());
|
|
assert(DstVNI && "Missing defined value");
|
|
assert(DstVNI->def == Idx.getDefIndex() && "Wrong copy def slot");
|
|
WorkList.push_back(std::make_pair(&DstLI, DstVNI));
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// Erase spills.
|
|
int FI;
|
|
if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
|
|
DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
|
|
// eliminateDeadDefs won't normally remove stores, so switch opcode.
|
|
MI->setDesc(TII.get(TargetOpcode::KILL));
|
|
DeadDefs.push_back(MI);
|
|
++NumRedundantSpills;
|
|
}
|
|
}
|
|
} while (!WorkList.empty());
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Rematerialization
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// markValueUsed - Remember that VNI failed to rematerialize, so its defining
|
|
/// instruction cannot be eliminated. See through snippet copies
|
|
void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
|
|
SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
|
|
WorkList.push_back(std::make_pair(LI, VNI));
|
|
do {
|
|
tie(LI, VNI) = WorkList.pop_back_val();
|
|
if (!UsedValues.insert(VNI))
|
|
continue;
|
|
|
|
if (VNI->isPHIDef()) {
|
|
MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
VNInfo *PVNI = LI->getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
|
|
if (PVNI)
|
|
WorkList.push_back(std::make_pair(LI, PVNI));
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// Follow snippet copies.
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
|
|
if (!SnippetCopies.count(MI))
|
|
continue;
|
|
LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
|
|
assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
|
|
VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getUseIndex());
|
|
assert(SnipVNI && "Snippet undefined before copy");
|
|
WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
|
|
} while (!WorkList.empty());
|
|
}
|
|
|
|
/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
|
|
bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
|
|
MachineBasicBlock::iterator MI) {
|
|
SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex();
|
|
VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
|
|
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << "\tadding <undef> flags: ");
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
|
|
MO.setIsUndef();
|
|
}
|
|
DEBUG(dbgs() << UseIdx << '\t' << *MI);
|
|
return true;
|
|
}
|
|
|
|
if (SnippetCopies.count(MI))
|
|
return false;
|
|
|
|
// Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
|
|
LiveRangeEdit::Remat RM(ParentVNI);
|
|
SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
|
|
if (SibI != SibValues.end())
|
|
RM.OrigMI = SibI->second.DefMI;
|
|
if (!Edit->canRematerializeAt(RM, UseIdx, false, LIS)) {
|
|
markValueUsed(&VirtReg, ParentVNI);
|
|
DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
|
|
return false;
|
|
}
|
|
|
|
// If the instruction also writes VirtReg.reg, it had better not require the
|
|
// same register for uses and defs.
|
|
bool Reads, Writes;
|
|
SmallVector<unsigned, 8> Ops;
|
|
tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
|
|
if (Writes) {
|
|
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(Ops[i]);
|
|
if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
|
|
markValueUsed(&VirtReg, ParentVNI);
|
|
DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Before rematerializing into a register for a single instruction, try to
|
|
// fold a load into the instruction. That avoids allocating a new register.
|
|
if (RM.OrigMI->getDesc().canFoldAsLoad() &&
|
|
foldMemoryOperand(MI, Ops, RM.OrigMI)) {
|
|
Edit->markRematerialized(RM.ParentVNI);
|
|
++NumFoldedLoads;
|
|
return true;
|
|
}
|
|
|
|
// Alocate a new register for the remat.
|
|
LiveInterval &NewLI = Edit->createFrom(Original, LIS, VRM);
|
|
NewLI.markNotSpillable();
|
|
|
|
// Finally we can rematerialize OrigMI before MI.
|
|
SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
|
|
LIS, TII, TRI);
|
|
DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
|
|
<< *LIS.getInstructionFromIndex(DefIdx));
|
|
|
|
// Replace operands
|
|
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(Ops[i]);
|
|
if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
|
|
MO.setReg(NewLI.reg);
|
|
MO.setIsKill();
|
|
}
|
|
}
|
|
DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
|
|
|
|
VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, LIS.getVNInfoAllocator());
|
|
NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
|
|
DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
|
|
++NumRemats;
|
|
return true;
|
|
}
|
|
|
|
/// reMaterializeAll - Try to rematerialize as many uses as possible,
|
|
/// and trim the live ranges after.
|
|
void InlineSpiller::reMaterializeAll() {
|
|
// analyzeSiblingValues has already tested all relevant defining instructions.
|
|
if (!Edit->anyRematerializable(LIS, TII, AA))
|
|
return;
|
|
|
|
UsedValues.clear();
|
|
|
|
// Try to remat before all uses of snippets.
|
|
bool anyRemat = false;
|
|
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
|
|
unsigned Reg = RegsToSpill[i];
|
|
LiveInterval &LI = LIS.getInterval(Reg);
|
|
for (MachineRegisterInfo::use_nodbg_iterator
|
|
RI = MRI.use_nodbg_begin(Reg);
|
|
MachineInstr *MI = RI.skipInstruction();)
|
|
anyRemat |= reMaterializeFor(LI, MI);
|
|
}
|
|
if (!anyRemat)
|
|
return;
|
|
|
|
// Remove any values that were completely rematted.
|
|
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
|
|
unsigned Reg = RegsToSpill[i];
|
|
LiveInterval &LI = LIS.getInterval(Reg);
|
|
for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
|
|
I != E; ++I) {
|
|
VNInfo *VNI = *I;
|
|
if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
|
|
continue;
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
|
|
MI->addRegisterDead(Reg, &TRI);
|
|
if (!MI->allDefsAreDead())
|
|
continue;
|
|
DEBUG(dbgs() << "All defs dead: " << *MI);
|
|
DeadDefs.push_back(MI);
|
|
}
|
|
}
|
|
|
|
// Eliminate dead code after remat. Note that some snippet copies may be
|
|
// deleted here.
|
|
if (DeadDefs.empty())
|
|
return;
|
|
DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
|
|
Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII);
|
|
|
|
// Get rid of deleted and empty intervals.
|
|
for (unsigned i = RegsToSpill.size(); i != 0; --i) {
|
|
unsigned Reg = RegsToSpill[i-1];
|
|
if (!LIS.hasInterval(Reg)) {
|
|
RegsToSpill.erase(RegsToSpill.begin() + (i - 1));
|
|
continue;
|
|
}
|
|
LiveInterval &LI = LIS.getInterval(Reg);
|
|
if (!LI.empty())
|
|
continue;
|
|
Edit->eraseVirtReg(Reg, LIS);
|
|
RegsToSpill.erase(RegsToSpill.begin() + (i - 1));
|
|
}
|
|
DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Spilling
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// If MI is a load or store of StackSlot, it can be removed.
|
|
bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
|
|
int FI = 0;
|
|
unsigned InstrReg;
|
|
if (!(InstrReg = TII.isLoadFromStackSlot(MI, FI)) &&
|
|
!(InstrReg = TII.isStoreToStackSlot(MI, FI)))
|
|
return false;
|
|
|
|
// We have a stack access. Is it the right register and slot?
|
|
if (InstrReg != Reg || FI != StackSlot)
|
|
return false;
|
|
|
|
DEBUG(dbgs() << "Coalescing stack access: " << *MI);
|
|
LIS.RemoveMachineInstrFromMaps(MI);
|
|
MI->eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
/// foldMemoryOperand - Try folding stack slot references in Ops into MI.
|
|
/// @param MI Instruction using or defining the current register.
|
|
/// @param Ops Operand indices from readsWritesVirtualRegister().
|
|
/// @param LoadMI Load instruction to use instead of stack slot when non-null.
|
|
/// @return True on success, and MI will be erased.
|
|
bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
MachineInstr *LoadMI) {
|
|
// TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
|
|
// operands.
|
|
SmallVector<unsigned, 8> FoldOps;
|
|
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
|
|
unsigned Idx = Ops[i];
|
|
MachineOperand &MO = MI->getOperand(Idx);
|
|
if (MO.isImplicit())
|
|
continue;
|
|
// FIXME: Teach targets to deal with subregs.
|
|
if (MO.getSubReg())
|
|
return false;
|
|
// We cannot fold a load instruction into a def.
|
|
if (LoadMI && MO.isDef())
|
|
return false;
|
|
// Tied use operands should not be passed to foldMemoryOperand.
|
|
if (!MI->isRegTiedToDefOperand(Idx))
|
|
FoldOps.push_back(Idx);
|
|
}
|
|
|
|
MachineInstr *FoldMI =
|
|
LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
|
|
: TII.foldMemoryOperand(MI, FoldOps, StackSlot);
|
|
if (!FoldMI)
|
|
return false;
|
|
LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
|
|
if (!LoadMI)
|
|
VRM.addSpillSlotUse(StackSlot, FoldMI);
|
|
MI->eraseFromParent();
|
|
DEBUG(dbgs() << "\tfolded: " << *FoldMI);
|
|
++NumFolded;
|
|
return true;
|
|
}
|
|
|
|
/// insertReload - Insert a reload of NewLI.reg before MI.
|
|
void InlineSpiller::insertReload(LiveInterval &NewLI,
|
|
SlotIndex Idx,
|
|
MachineBasicBlock::iterator MI) {
|
|
MachineBasicBlock &MBB = *MI->getParent();
|
|
TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
|
|
MRI.getRegClass(NewLI.reg), &TRI);
|
|
--MI; // Point to load instruction.
|
|
SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
|
|
VRM.addSpillSlotUse(StackSlot, MI);
|
|
DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
|
|
VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0,
|
|
LIS.getVNInfoAllocator());
|
|
NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
|
|
++NumReloads;
|
|
}
|
|
|
|
/// insertSpill - Insert a spill of NewLI.reg after MI.
|
|
void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
|
|
SlotIndex Idx, MachineBasicBlock::iterator MI) {
|
|
MachineBasicBlock &MBB = *MI->getParent();
|
|
TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
|
|
MRI.getRegClass(NewLI.reg), &TRI);
|
|
--MI; // Point to store instruction.
|
|
SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
|
|
VRM.addSpillSlotUse(StackSlot, MI);
|
|
DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
|
|
VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, LIS.getVNInfoAllocator());
|
|
NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
|
|
++NumSpills;
|
|
}
|
|
|
|
/// spillAroundUses - insert spill code around each use of Reg.
|
|
void InlineSpiller::spillAroundUses(unsigned Reg) {
|
|
DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
|
|
LiveInterval &OldLI = LIS.getInterval(Reg);
|
|
|
|
// Iterate over instructions using Reg.
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
|
|
MachineInstr *MI = RI.skipInstruction();) {
|
|
|
|
// Debug values are not allowed to affect codegen.
|
|
if (MI->isDebugValue()) {
|
|
// Modify DBG_VALUE now that the value is in a spill slot.
|
|
uint64_t Offset = MI->getOperand(1).getImm();
|
|
const MDNode *MDPtr = MI->getOperand(2).getMetadata();
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
if (MachineInstr *NewDV = TII.emitFrameIndexDebugValue(MF, StackSlot,
|
|
Offset, MDPtr, DL)) {
|
|
DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
MBB->insert(MBB->erase(MI), NewDV);
|
|
} else {
|
|
DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
|
|
MI->eraseFromParent();
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// Ignore copies to/from snippets. We'll delete them.
|
|
if (SnippetCopies.count(MI))
|
|
continue;
|
|
|
|
// Stack slot accesses may coalesce away.
|
|
if (coalesceStackAccess(MI, Reg))
|
|
continue;
|
|
|
|
// Analyze instruction.
|
|
bool Reads, Writes;
|
|
SmallVector<unsigned, 8> Ops;
|
|
tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);
|
|
|
|
// Find the slot index where this instruction reads and writes OldLI.
|
|
// This is usually the def slot, except for tied early clobbers.
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
|
|
if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getUseIndex()))
|
|
if (SlotIndex::isSameInstr(Idx, VNI->def))
|
|
Idx = VNI->def;
|
|
|
|
// Check for a sibling copy.
|
|
unsigned SibReg = isFullCopyOf(MI, Reg);
|
|
if (SibReg && isSibling(SibReg)) {
|
|
// This may actually be a copy between snippets.
|
|
if (isRegToSpill(SibReg)) {
|
|
DEBUG(dbgs() << "Found new snippet copy: " << *MI);
|
|
SnippetCopies.insert(MI);
|
|
continue;
|
|
}
|
|
if (Writes) {
|
|
// Hoist the spill of a sib-reg copy.
|
|
if (hoistSpill(OldLI, MI)) {
|
|
// This COPY is now dead, the value is already in the stack slot.
|
|
MI->getOperand(0).setIsDead();
|
|
DeadDefs.push_back(MI);
|
|
continue;
|
|
}
|
|
} else {
|
|
// This is a reload for a sib-reg copy. Drop spills downstream.
|
|
LiveInterval &SibLI = LIS.getInterval(SibReg);
|
|
eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
|
|
// The COPY will fold to a reload below.
|
|
}
|
|
}
|
|
|
|
// Attempt to fold memory ops.
|
|
if (foldMemoryOperand(MI, Ops))
|
|
continue;
|
|
|
|
// Allocate interval around instruction.
|
|
// FIXME: Infer regclass from instruction alone.
|
|
LiveInterval &NewLI = Edit->createFrom(Reg, LIS, VRM);
|
|
NewLI.markNotSpillable();
|
|
|
|
if (Reads)
|
|
insertReload(NewLI, Idx, MI);
|
|
|
|
// Rewrite instruction operands.
|
|
bool hasLiveDef = false;
|
|
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(Ops[i]);
|
|
MO.setReg(NewLI.reg);
|
|
if (MO.isUse()) {
|
|
if (!MI->isRegTiedToDefOperand(Ops[i]))
|
|
MO.setIsKill();
|
|
} else {
|
|
if (!MO.isDead())
|
|
hasLiveDef = true;
|
|
}
|
|
}
|
|
DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
|
|
|
|
// FIXME: Use a second vreg if instruction has no tied ops.
|
|
if (Writes && hasLiveDef)
|
|
insertSpill(NewLI, OldLI, Idx, MI);
|
|
|
|
DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
|
|
}
|
|
}
|
|
|
|
/// spillAll - Spill all registers remaining after rematerialization.
|
|
void InlineSpiller::spillAll() {
|
|
// Update LiveStacks now that we are committed to spilling.
|
|
if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
|
|
StackSlot = VRM.assignVirt2StackSlot(Original);
|
|
StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
|
|
StackInt->getNextValue(SlotIndex(), 0, LSS.getVNInfoAllocator());
|
|
} else
|
|
StackInt = &LSS.getInterval(StackSlot);
|
|
|
|
if (Original != Edit->getReg())
|
|
VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
|
|
|
|
assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
|
|
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
|
|
StackInt->MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
|
|
StackInt->getValNumInfo(0));
|
|
DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
|
|
|
|
// Spill around uses of all RegsToSpill.
|
|
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
|
|
spillAroundUses(RegsToSpill[i]);
|
|
|
|
// Hoisted spills may cause dead code.
|
|
if (!DeadDefs.empty()) {
|
|
DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
|
|
Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII);
|
|
}
|
|
|
|
// Finally delete the SnippetCopies.
|
|
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(RegsToSpill[i]);
|
|
MachineInstr *MI = RI.skipInstruction();) {
|
|
assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
|
|
// FIXME: Do this with a LiveRangeEdit callback.
|
|
VRM.RemoveMachineInstrFromMaps(MI);
|
|
LIS.RemoveMachineInstrFromMaps(MI);
|
|
MI->eraseFromParent();
|
|
}
|
|
}
|
|
|
|
// Delete all spilled registers.
|
|
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
|
|
Edit->eraseVirtReg(RegsToSpill[i], LIS);
|
|
}
|
|
|
|
void InlineSpiller::spill(LiveRangeEdit &edit) {
|
|
++NumSpilledRanges;
|
|
Edit = &edit;
|
|
assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
|
|
&& "Trying to spill a stack slot.");
|
|
// Share a stack slot among all descendants of Original.
|
|
Original = VRM.getOriginal(edit.getReg());
|
|
StackSlot = VRM.getStackSlot(Original);
|
|
StackInt = 0;
|
|
|
|
DEBUG(dbgs() << "Inline spilling "
|
|
<< MRI.getRegClass(edit.getReg())->getName()
|
|
<< ':' << edit.getParent() << "\nFrom original "
|
|
<< LIS.getInterval(Original) << '\n');
|
|
assert(edit.getParent().isSpillable() &&
|
|
"Attempting to spill already spilled value.");
|
|
assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
|
|
|
|
collectRegsToSpill();
|
|
analyzeSiblingValues();
|
|
reMaterializeAll();
|
|
|
|
// Remat may handle everything.
|
|
if (!RegsToSpill.empty())
|
|
spillAll();
|
|
|
|
Edit->calculateRegClassAndHint(MF, LIS, Loops);
|
|
}
|