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https://github.com/c64scene-ar/llvm-6502.git
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27b1252c13
This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.0 KiB
LLVM
77 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=arm -mattr=+v6t2 %s -o - | FileCheck %s
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%struct.F = type { [3 x i8], i8 }
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@X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1]
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define void @f1([1 x i32] %f.coerce0) nounwind {
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entry:
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; CHECK: f1
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; CHECK: mov r2, #10
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; CHECK: bfi r1, r2, #22, #4
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%0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
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%1 = and i32 %0, -62914561 ; <i32> [#uses=1]
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%2 = or i32 %1, 41943040 ; <i32> [#uses=1]
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store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
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ret void
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}
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define i32 @f2(i32 %A, i32 %B) nounwind {
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entry:
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; CHECK: f2
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; CHECK: lsr{{.*}}#7
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; CHECK: bfi r0, r1, #7, #16
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%and = and i32 %A, -8388481 ; <i32> [#uses=1]
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%and2 = and i32 %B, 8388480 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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define i32 @f3(i32 %A, i32 %B) nounwind {
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entry:
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; CHECK: f3
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; CHECK: lsr{{.*}} #7
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; CHECK: bfi {{.*}}, #7, #16
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%and = and i32 %A, 8388480 ; <i32> [#uses=1]
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%and2 = and i32 %B, -8388481 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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; rdar://8752056
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define i32 @f4(i32 %a) nounwind {
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; CHECK: f4
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; CHECK: movw [[R1:r[0-9]+]], #3137
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; CHECK: bfi [[R1]], {{r[0-9]+}}, #15, #5
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%1 = shl i32 %a, 15
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%ins7 = and i32 %1, 1015808
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%ins12 = or i32 %ins7, 3137
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ret i32 %ins12
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}
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; rdar://8458663
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define i32 @f5(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: f5:
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; CHECK-NOT: bfc
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; CHECK: bfi r0, r1, #20, #4
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%0 = and i32 %a, -15728641
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%1 = shl i32 %b, 20
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%2 = and i32 %1, 15728640
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%3 = or i32 %2, %0
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ret i32 %3
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}
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; rdar://9609030
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define i32 @f6(i32 %a, i32 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f6:
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; CHECK-NOT: bic
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; CHECK: bfi r0, r1, #8, #9
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%and = and i32 %a, -130817
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%and2 = shl i32 %b, 8
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%shl = and i32 %and2, 130816
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%or = or i32 %shl, %and
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ret i32 %or
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}
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