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https://github.com/c64scene-ar/llvm-6502.git
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01d8611240
The coalescer is very aggressive at propagating constraints on the register classes, and the register allocator doesn’t know how to split sub-registers later to recover. This patch provides an escape valve for targets that encounter this problem to limit coalescing. This patch also implements such for ARM to lower register pressure when using lots of large register classes. This works around PR18825. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213078 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
2.2 KiB
LLVM
43 lines
2.2 KiB
LLVM
; RUN: llc -O3 %s -o - | FileCheck %s
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; ModuleID = 'fo.c'
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:32-n8:16:32-S64"
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target triple = "thumbv7-none-linux-gnueabi"
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; CHECK: vpush
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; CHECK: vpop
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define void @foo(float* nocapture %A) #0 {
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%1= bitcast float* %A to i8*
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%2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32(i8* %1, i32 4)
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%3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 0
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%divp_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %3
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%4 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 1
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%div3p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %4
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%5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 2
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%div8p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %5
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%6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 3
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%div13p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %6
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tail call void @llvm.arm.neon.vst4.v4f32(i8* %1, <4 x float> %divp_vec, <4 x float> %div3p_vec, <4 x float> %div8p_vec, <4 x float> %div13p_vec, i32 4)
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ret void
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}
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; Function Attrs: nounwind
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declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1
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; Function Attrs: nounwind readonly
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; Function Attrs: nounwind
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declare void @llvm.arm.neon.vst4.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) #1
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declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32(i8*, i32) #2
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; Function Attrs: nounwind
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readonly }
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!llvm.ident = !{!0}
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!0 = metadata !{metadata !"Snapdragon LLVM ARM Compiler 3.4"}
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!1 = metadata !{metadata !1}
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