mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203433 91177308-0d34-0410-b5e6-96231b3b80d8
263 lines
8.6 KiB
C++
263 lines
8.6 KiB
C++
//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARMTargetMachine.h"
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#include "ARM.h"
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#include "ARMFrameLowering.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
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cl::desc("Inhibit optimization of S->D register accesses on A15"),
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cl::init(false));
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extern "C" void LLVMInitializeARMTarget() {
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// Register the target.
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RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
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RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
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}
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/// TargetMachine ctor - Create an ARM architecture model.
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///
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ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, Options),
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JITInfo(),
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InstrItins(Subtarget.getInstrItineraryData()) {
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// Default to triple-appropriate float ABI
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if (Options.FloatABIType == FloatABI::Default)
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this->Options.FloatABIType =
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Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
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}
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void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our ARM pass. This
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// allows the ARM pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createARMTargetTransformInfoPass(this));
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}
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void ARMTargetMachine::anchor() { }
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static std::string computeDataLayout(ARMSubtarget &ST) {
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// Little endian.
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std::string Ret = "e";
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Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
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// Pointers are 32 bits and aligned to 32 bits.
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Ret += "-p:32:32";
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// On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
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// align to 32.
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if (ST.isThumb())
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Ret += "-i1:8:32-i8:8:32-i16:16:32";
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// ABIs other than APC have 64 bit integers with natural alignment.
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if (!ST.isAPCS_ABI())
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Ret += "-i64:64";
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// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
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// bits, others to 64 bits. We always try to align to 64 bits.
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if (ST.isAPCS_ABI())
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Ret += "-f64:32:64";
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// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
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// to 64. We always ty to give them natural alignment.
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if (ST.isAPCS_ABI())
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Ret += "-v64:32:64-v128:32:128";
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else
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Ret += "-v128:64:128";
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// On thumb and APCS, only try to align aggregates to 32 bits (the default is
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// 64 bits).
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if (ST.isThumb() || ST.isAPCS_ABI())
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Ret += "-a:0:32";
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// Integer registers are 32 bits.
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Ret += "-n32";
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// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
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// aligned everywhere else.
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if (ST.isTargetNaCl())
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Ret += "-S128";
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else if (ST.isAAPCS_ABI())
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Ret += "-S64";
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else
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Ret += "-S32";
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return Ret;
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}
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ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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InstrInfo(Subtarget),
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DL(computeDataLayout(Subtarget)),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget) {
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initAsmInfo();
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if (!Subtarget.hasARMOps())
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report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
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"support ARM mode execution!");
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}
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void ThumbTargetMachine::anchor() { }
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ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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InstrInfo(Subtarget.hasThumb2()
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? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
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: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
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DL(computeDataLayout(Subtarget)),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget.hasThumb2()
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? new ARMFrameLowering(Subtarget)
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: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
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initAsmInfo();
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}
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namespace {
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/// ARM Code Generator Pass Configuration Options.
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class ARMPassConfig : public TargetPassConfig {
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public:
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ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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ARMBaseTargetMachine &getARMTargetMachine() const {
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return getTM<ARMBaseTargetMachine>();
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}
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const ARMSubtarget &getARMSubtarget() const {
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return *getARMTargetMachine().getSubtargetImpl();
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}
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addPreRegAlloc() override;
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bool addPreSched2() override;
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bool addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new ARMPassConfig(this, PM);
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}
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bool ARMPassConfig::addPreISel() {
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createGlobalMergePass(TM));
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return false;
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}
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bool ARMPassConfig::addInstSelector() {
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addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
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const ARMSubtarget *Subtarget = &getARMSubtarget();
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if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
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TM->Options.EnableFastISel)
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addPass(createARMGlobalBaseRegPass());
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return false;
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}
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bool ARMPassConfig::addPreRegAlloc() {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
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addPass(createARMLoadStoreOptimizationPass(true));
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if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
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addPass(createMLxExpansionPass());
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// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
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// enabled when NEON is available.
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if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
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getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
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addPass(createA15SDOptimizerPass());
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}
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return true;
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}
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bool ARMPassConfig::addPreSched2() {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (getOptLevel() != CodeGenOpt::None) {
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if (!getARMSubtarget().isThumb1Only()) {
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addPass(createARMLoadStoreOptimizationPass());
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printAndVerify("After ARM load / store optimizer");
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}
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if (getARMSubtarget().hasNEON())
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addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
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}
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// Expand some pseudo instructions into multiple instructions to allow
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// proper scheduling.
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addPass(createARMExpandPseudoPass());
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if (getOptLevel() != CodeGenOpt::None) {
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if (!getARMSubtarget().isThumb1Only()) {
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// in v8, IfConversion depends on Thumb instruction widths
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if (getARMSubtarget().restrictIT() &&
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!getARMSubtarget().prefers32BitThumb())
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addPass(createThumb2SizeReductionPass());
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addPass(&IfConverterID);
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}
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}
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if (getARMSubtarget().isThumb2())
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addPass(createThumb2ITBlockPass());
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return true;
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}
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bool ARMPassConfig::addPreEmitPass() {
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if (getARMSubtarget().isThumb2()) {
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if (!getARMSubtarget().prefers32BitThumb())
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addPass(createThumb2SizeReductionPass());
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// Constant island pass work on unbundled instructions.
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addPass(&UnpackMachineBundlesID);
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}
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addPass(createARMConstantIslandPass());
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return true;
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}
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bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for ARM.
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PM.add(createARMJITCodeEmitterPass(*this, JCE));
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return false;
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}
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