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llvm-6502/test/MC/Disassembler
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Adam Nemet f36c3de849 [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields 
V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and
NDS register fields.  This was simply not used in the decoder until now.

Fixes <rdar://problem/17402661>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 01:42:32 +00:00
..
AArch64 Condition codes AL and NV are invalid in the aliases that use 2014-06-10 13:11:35 +00:00
ARM ARM: honor hex immediate formatting for ldr/str i12 offsets. 2014-06-11 20:26:45 +00:00
Mips [mips][mips64r6] Add BLTC and BLTUC instructions 2014-06-18 14:36:00 +00:00
PowerPC Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
Sparc Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
SystemZ Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
X86 [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields 2014-06-24 01:42:32 +00:00
XCore Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00