llvm-6502/test/CodeGen/ARM/peephole-bitcast.ll
Evan Cheng d158fba3e4 Add a peephole optimization to optimize pairs of bitcasts. e.g.
v2 = bitcast v1
...
v3 = bitcast v2
...
   = v3
=>
v2 = bitcast v1
...
   = v1
if v1 and v3 are of in the same register class.

bitcast between i32 and fp (and others) are often not nops since they
are in different register classes. These bitcast instructions are often
left because they are in different basic blocks and cannot be
eliminated by dag combine.

rdar://9104514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 05:13:13 +00:00

24 lines
608 B
LLVM

; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
; vmov s0, r0 + vmov r0, s0 should have been optimized away.
; rdar://9104514
define void @t(float %x) nounwind ssp {
entry:
; CHECK: t:
; CHECK-NOT: vmov
; CHECK: bl
%0 = bitcast float %x to i32
%cmp = icmp ult i32 %0, 2139095039
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @doSomething(float %x) nounwind
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
declare void @doSomething(float)