mirror of
https://github.com/c64scene-ar/llvm-6502.git
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only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46483 91177308-0d34-0410-b5e6-96231b3b80d8
178 lines
3.3 KiB
LLVM
178 lines
3.3 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
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; RUN: grep shufb %t1.s | count 27
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; RUN: grep lqa %t1.s | count 27
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; RUN: grep lqd %t2.s | count 27
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; RUN: grep space %t1.s | count 8
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; RUN: grep byte %t1.s | count 424
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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define i32 @i32_extract_0(<4 x i32> %v) {
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entry:
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%a = extractelement <4 x i32> %v, i32 0
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ret i32 %a
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}
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define i32 @i32_extract_1(<4 x i32> %v) {
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entry:
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%a = extractelement <4 x i32> %v, i32 1
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ret i32 %a
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}
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define i32 @i32_extract_2(<4 x i32> %v) {
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entry:
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%a = extractelement <4 x i32> %v, i32 2
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ret i32 %a
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}
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define i32 @i32_extract_3(<4 x i32> %v) {
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entry:
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%a = extractelement <4 x i32> %v, i32 3
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ret i32 %a
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}
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define i16 @i16_extract_0(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 0
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ret i16 %a
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}
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define i16 @i16_extract_1(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 1
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ret i16 %a
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}
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define i16 @i16_extract_2(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 2
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ret i16 %a
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}
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define i16 @i16_extract_3(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 3
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ret i16 %a
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}
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define i16 @i16_extract_4(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 4
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ret i16 %a
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}
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define i16 @i16_extract_5(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 5
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ret i16 %a
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}
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define i16 @i16_extract_6(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 6
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ret i16 %a
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}
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define i16 @i16_extract_7(<8 x i16> %v) {
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entry:
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%a = extractelement <8 x i16> %v, i32 7
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ret i16 %a
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}
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define i8 @i8_extract_0(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 0
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ret i8 %a
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}
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define i8 @i8_extract_1(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 1
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ret i8 %a
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}
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define i8 @i8_extract_2(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 2
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ret i8 %a
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}
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define i8 @i8_extract_3(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 3
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ret i8 %a
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}
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define i8 @i8_extract_4(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 4
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ret i8 %a
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}
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define i8 @i8_extract_5(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 5
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ret i8 %a
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}
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define i8 @i8_extract_6(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 6
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ret i8 %a
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}
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define i8 @i8_extract_7(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 7
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ret i8 %a
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}
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define i8 @i8_extract_8(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 8
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ret i8 %a
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}
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define i8 @i8_extract_9(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 9
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ret i8 %a
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}
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define i8 @i8_extract_10(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 10
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ret i8 %a
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}
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define i8 @i8_extract_11(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 11
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ret i8 %a
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}
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define i8 @i8_extract_12(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 12
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ret i8 %a
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}
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define i8 @i8_extract_13(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 13
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ret i8 %a
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}
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define i8 @i8_extract_14(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 14
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ret i8 %a
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}
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define i8 @i8_extract_15(<16 x i8> %v) {
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entry:
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%a = extractelement <16 x i8> %v, i32 15
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ret i8 %a
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}
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