llvm-6502/test/CodeGen
Andrea Di Biagio a1e1f01699 [X86] Improved target specific combine on VSELECT dag nodes.
This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to
convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1.
On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd.

Also, removed a target specific combine that performed a premature lowering of
VSELECT nodes to target specific MOVSS/MOVSD nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222647 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 12:23:15 +00:00
..
AArch64 DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same divisor info FMULs by the reciprocal. 2014-11-21 06:39:58 +00:00
ARM
CPP
Generic
Hexagon
Inputs
Mips [mips][microMIPS] This patch implements functionality in MIPS delay slot 2014-11-21 22:04:35 +00:00
MSP430
NVPTX
PowerPC [PPC] Use SeparateConstOffsetFromGEP 2014-11-21 04:35:51 +00:00
R600 R600: Fix extloads of i1 on R600/Evergreen 2014-11-23 02:57:54 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [X86] Improved target specific combine on VSELECT dag nodes. 2014-11-24 12:23:15 +00:00
XCore