mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1edd1a336a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188626 91177308-0d34-0410-b5e6-96231b3b80d8
282 lines
8.5 KiB
C++
282 lines
8.5 KiB
C++
//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SIInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIDefines.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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using namespace llvm;
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SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm)
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{ }
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const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
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return RI;
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}
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void
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SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// If we are trying to copy to or from SCC, there is a bug somewhere else in
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// the backend. While it may be theoretically possible to do this, it should
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// never be necessary.
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assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
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static const int16_t Sub0_15[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
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AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
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AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
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};
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static const int16_t Sub0_7[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
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};
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static const int16_t Sub0_3[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
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};
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static const int16_t Sub0_2[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
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};
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static const int16_t Sub0_1[] = {
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AMDGPU::sub0, AMDGPU::sub1, 0
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};
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unsigned Opcode;
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const int16_t *SubIndices;
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if (AMDGPU::M0 == DestReg) {
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// Check if M0 isn't already set to this value
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for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
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I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
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if (!I->definesRegister(AMDGPU::M0))
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continue;
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unsigned Opc = I->getOpcode();
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if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
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break;
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if (!I->readsRegister(SrcReg))
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break;
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// The copy isn't necessary
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return;
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}
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}
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if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_15;
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} else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
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AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
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AMDGPU::SReg_64RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_1;
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} else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_2;
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} else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
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AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
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AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
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AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_15;
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} else {
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llvm_unreachable("Can't copy register!");
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}
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while (unsigned SubIdx = *SubIndices++) {
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MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
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get(Opcode), RI.getSubReg(DestReg, SubIdx));
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Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
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if (*SubIndices)
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Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
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}
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}
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unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
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int NewOpc;
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// Try to map original to commuted opcode
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if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
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return NewOpc;
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// Try to map commuted to original opcode
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if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
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return NewOpc;
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return Opcode;
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}
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MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg() ||
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!MI->getOperand(2).isReg())
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return 0;
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MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
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if (MI)
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MI->setDesc(get(commuteOpcode(MI->getOpcode())));
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return MI;
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}
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MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const {
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MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_B32_e32), DebugLoc());
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MachineInstrBuilder MIB(*MF, MI);
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MIB.addReg(DstReg, RegState::Define);
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MIB.addImm(Imm);
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return MI;
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}
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bool SIInstrInfo::isMov(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::S_MOV_B32:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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return true;
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}
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}
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bool
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SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return RC != &AMDGPU::EXECRegRegClass;
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}
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int SIInstrInfo::isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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int SIInstrInfo::isSMRD(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SMRD;
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}
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//===----------------------------------------------------------------------===//
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// Indirect addressing callbacks
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//===----------------------------------------------------------------------===//
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unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const {
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assert(Channel == 0);
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return RegIndex;
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}
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int SIInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
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llvm_unreachable("Unimplemented");
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}
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int SIInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
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llvm_unreachable("Unimplemented");
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}
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const TargetRegisterClass *SIInstrInfo::getIndirectAddrStoreRegClass(
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unsigned SourceReg) const {
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llvm_unreachable("Unimplemented");
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}
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const TargetRegisterClass *SIInstrInfo::getIndirectAddrLoadRegClass() const {
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llvm_unreachable("Unimplemented");
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}
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MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address, unsigned OffsetReg) const {
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llvm_unreachable("Unimplemented");
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}
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MachineInstrBuilder SIInstrInfo::buildIndirectRead(
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address, unsigned OffsetReg) const {
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llvm_unreachable("Unimplemented");
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}
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const TargetRegisterClass *SIInstrInfo::getSuperIndirectRegClass() const {
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llvm_unreachable("Unimplemented");
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}
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