Andrew Trick c8bfd1d78f Convert -enable-sched-cycles and -enable-sched-hazard to -disable ... flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8		2011-01-21 05:51:33 +00:00
..
Mangler.h
SubtargetFeature.h
Target.td	Do not model all INLINEASM instructions as having unmodelled side effects.	2011-01-07 23:50:32 +00:00
TargetAsmBackend.h	Remove the MCObjectFormat class.	2010-12-18 05:37:28 +00:00
TargetAsmInfo.h	Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.	2011-01-10 12:39:04 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.h
TargetCallingConv.td
TargetData.h	fix typo	2011-01-15 06:27:35 +00:00
TargetELFWriterInfo.h
TargetFrameLowering.h	Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.	2011-01-10 12:39:04 +00:00
TargetInstrDesc.h
TargetInstrInfo.h	Convert -enable-sched-cycles and -enable-sched-hazard to -disable	2011-01-21 05:51:33 +00:00
TargetInstrItineraries.h	Various bits of framework needed for precise machine-level selection	2010-12-24 05:03:26 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy	2011-01-06 06:52:41 +00:00
TargetLoweringObjectFile.h
TargetMachine.h	Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.	2011-01-10 12:39:04 +00:00
TargetOpcodes.h
TargetOptions.h
TargetRegisterInfo.h	Remove TargetRegisterInfo::NoRegister.	2011-01-09 23:20:48 +00:00
TargetRegistry.h
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td	Add ARM patterns to match EXTRACT_SUBVECTOR nodes.	2011-01-07 04:59:04 +00:00
TargetSelectionDAGInfo.h
TargetSubtarget.h