Andrew Trick d1dace8aea Enable support for precise scheduling of the instruction selection ... DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8		2011-01-21 06:19:05 +00:00
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CodeGen	Enable support for precise scheduling of the instruction selection	2011-01-21 06:19:05 +00:00
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Target	Convert -enable-sched-cycles and -enable-sched-hazard to -disable	2011-01-21 05:51:33 +00:00
Transforms	fix PR9013, an infinite loop in instcombine.	2011-01-21 05:29:50 +00:00
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