llvm-6502/test/CodeGen
Scott Michel d1e8d9c0a5 CellSPU:
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-21 04:58:48 +00:00
..
Alpha Fix Alpha test and support for private linkage. 2009-01-15 21:51:46 +00:00
ARM Add the private linkage. 2009-01-15 20:18:42 +00:00
CBackend
CellSPU CellSPU: 2009-01-21 04:58:48 +00:00
CPP
Generic Don't bother running the assembler, we don't know that it will be configured 2009-01-20 21:41:53 +00:00
IA64 Add the private linkage. 2009-01-15 20:18:42 +00:00
Mips Add the private linkage. 2009-01-15 20:18:42 +00:00
PowerPC Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's. 2009-01-16 22:57:32 +00:00
SPARC Add the private linkage. 2009-01-15 20:18:42 +00:00
X86 Favors generating "not" over "xor -1". For example. 2009-01-21 02:09:05 +00:00
XCore Add the private linkage. 2009-01-15 20:18:42 +00:00