llvm-6502/lib/Target/Sparc
Jakob Stoklund Olesen fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
..
AsmPrinter Momentous day: remove the "O" member from AsmPrinter. Now all 2010-04-04 08:18:47 +00:00
TargetInfo
CMakeLists.txt
DelaySlotFiller.cpp use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() 2010-04-02 20:16:16 +00:00
FPMover.cpp
Makefile
README.txt
Sparc.h
Sparc.td Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. 2010-04-05 03:10:20 +00:00
SparcCallingConv.td
SparcInstrFormats.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcInstrInfo.cpp use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() 2010-04-02 20:16:16 +00:00
SparcInstrInfo.h
SparcInstrInfo.td tidy up 2010-03-18 23:57:57 +00:00
SparcISelDAGToDAG.cpp Sink InstructionSelect() out of each target into SDISel, and rename it 2010-03-02 06:34:30 +00:00
SparcISelLowering.cpp
SparcISelLowering.h
SparcMachineFunctionInfo.h
SparcMCAsmInfo.cpp eliminate the magic AbsoluteDebugSectionOffsets MAI hook, 2010-04-04 23:22:29 +00:00
SparcMCAsmInfo.h
SparcRegisterInfo.cpp use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() 2010-04-02 20:16:16 +00:00
SparcRegisterInfo.h Change the Value argument to eliminateFrameIndex to a type-tagged value. This 2010-03-09 21:45:49 +00:00
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support