llvm-6502/test/CodeGen
Tom Stellard d2442c10f9 R600/SI: Add double precision fsub pattern for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:15:08 +00:00
..
AArch64 Start using CHECK-LABEL in some tests. 2013-07-12 14:54:12 +00:00
ARM Start using CHECK-LABEL in some tests. 2013-07-12 14:54:12 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips
MSP430
NVPTX
PowerPC Start using CHECK-LABEL in some tests. 2013-07-12 14:54:12 +00:00
R600 R600/SI: Add double precision fsub pattern for SI 2013-07-12 18:15:08 +00:00
SI
SPARC
SystemZ [SystemZ] Add test missing from r186148 2013-07-12 09:20:14 +00:00
Thumb
Thumb2 ARM: Fix incorrect pack pattern for thumb2 2013-07-09 22:59:22 +00:00
X86 X86: Shrink certain forms of movsx. 2013-07-12 18:06:44 +00:00
XCore