mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148455 91177308-0d34-0410-b5e6-96231b3b80d8
617 lines
22 KiB
C++
617 lines
22 KiB
C++
//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "MCTargetDesc/ARMFixupKinds.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class ARMELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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ARMELFObjectWriter(uint8_t OSABI)
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: MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
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/*HasRelocationAddend*/ false) {}
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};
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class ARMAsmBackend : public MCAsmBackend {
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const MCSubtargetInfo* STI;
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bool isThumbMode; // Currently emitting Thumb code.
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public:
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ARMAsmBackend(const Target &T, const StringRef TT)
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: MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
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isThumbMode(TT.startswith("thumb")) {}
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~ARMAsmBackend() {
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delete STI;
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}
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unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
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bool hasNOP() const {
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return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// ARMFixupKinds.h.
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//
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// Name Offset (bits) Size (bits) Flags
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{ "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
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// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
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{ "fixup_arm_movt_hi16", 0, 20, 0 },
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{ "fixup_arm_movw_lo16", 0, 20, 0 },
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{ "fixup_t2_movt_hi16", 0, 20, 0 },
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{ "fixup_t2_movw_lo16", 0, 20, 0 },
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{ "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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/// processFixupValue - Target hook to process the literal value of a fixup
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/// if necessary.
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void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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MCValue &Target, uint64_t &Value) {
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// Some fixups to thumb function symbols need the low bit (thumb bit)
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// twiddled.
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if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
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(unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
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(unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
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if (const MCSymbolRefExpr *A = Target.getSymA()) {
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const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
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if (Asm.isThumbFunc(&Sym))
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Value |= 1;
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}
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}
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}
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bool mayNeedRelaxation(const MCInst &Inst) const;
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCInstFragment *DF,
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const MCAsmLayout &Layout) const;
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
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void handleAssemblerFlag(MCAssemblerFlag Flag) {
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switch (Flag) {
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default: break;
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case MCAF_Code16:
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setIsThumb(true);
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break;
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case MCAF_Code32:
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setIsThumb(false);
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break;
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}
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}
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unsigned getPointerSize() const { return 4; }
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bool isThumb() const { return isThumbMode; }
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void setIsThumb(bool it) { isThumbMode = it; }
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};
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} // end anonymous namespace
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static unsigned getRelaxedOpcode(unsigned Op) {
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switch (Op) {
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default: return Op;
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case ARM::tBcc: return ARM::t2Bcc;
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case ARM::tLDRpciASM: return ARM::t2LDRpci;
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}
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}
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bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
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if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
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return true;
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return false;
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}
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bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCInstFragment *DF,
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const MCAsmLayout &Layout) const {
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switch (Fixup.getKind()) {
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default: assert(0 && "Unexpected fixup kind in fixupNeedsRelaxation()!");
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case ARM::fixup_arm_thumb_bcc: {
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// Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
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// low bit being an implied zero. There's an implied +4 offset for the
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// branch, so we adjust the other way here to determine what's
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// encodable.
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//
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// Relax if the value is too big for a (signed) i8.
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int64_t Offset = int64_t(Value) - 4;
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return Offset > 254 || Offset < -256;
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}
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case ARM::fixup_arm_thumb_cp: {
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// If the immediate is negative, greater than 1020, or not a multiple
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// of four, the wide version of the instruction must be used.
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int64_t Offset = int64_t(Value) - 4;
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return Offset > 1020 || Offset < 0 || Offset & 3;
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}
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}
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llvm_unreachable("Invalid switch/cash!?");
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}
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void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
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// Sanity check w/ diagnostic if we get here w/ a bogus instruction.
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if (RelaxedOp == Inst.getOpcode()) {
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SmallString<256> Tmp;
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raw_svector_ostream OS(Tmp);
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Inst.dump_pretty(OS);
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OS << "\n";
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report_fatal_error("unexpected instruction to relax: " + OS.str());
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}
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// The instructions we're relaxing have (so far) the same operands.
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// We just need to update to the proper opcode.
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Res = Inst;
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Res.setOpcode(RelaxedOp);
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}
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bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
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const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
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const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
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const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
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if (isThumb()) {
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const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
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: Thumb1_16bitNopEncoding;
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uint64_t NumNops = Count / 2;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write16(nopEncoding);
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if (Count & 1)
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OW->Write8(0);
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return true;
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}
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// ARM mode
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const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
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: ARMv4_NopEncoding;
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write32(nopEncoding);
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// FIXME: should this function return false when unable to write exactly
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// 'Count' bytes with NOP encodings?
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switch (Count % 4) {
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default: break; // No leftover bytes to write
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case 1: OW->Write8(0); break;
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case 2: OW->Write16(0); break;
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case 3: OW->Write16(0); OW->Write8(0xa0); break;
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}
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return true;
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}
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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return Value;
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case ARM::fixup_arm_movt_hi16:
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Value >>= 16;
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// Fallthrough
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case ARM::fixup_arm_movw_lo16:
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case ARM::fixup_arm_movt_hi16_pcrel:
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case ARM::fixup_arm_movw_lo16_pcrel: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned Lo12 = Value & 0x0FFF;
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// inst{19-16} = Hi4;
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// inst{11-0} = Lo12;
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Value = (Hi4 << 16) | (Lo12);
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return Value;
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}
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case ARM::fixup_t2_movt_hi16:
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Value >>= 16;
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// Fallthrough
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case ARM::fixup_t2_movw_lo16:
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case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
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// the other hi16 fixup?
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case ARM::fixup_t2_movw_lo16_pcrel: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned i = (Value & 0x800) >> 11;
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unsigned Mid3 = (Value & 0x700) >> 8;
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unsigned Lo8 = Value & 0x0FF;
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// inst{19-16} = Hi4;
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// inst{26} = i;
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// inst{14-12} = Mid3;
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// inst{7-0} = Lo8;
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Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
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uint64_t swapped = (Value & 0xFFFF0000) >> 16;
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swapped |= (Value & 0x0000FFFF) << 16;
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return swapped;
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}
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case ARM::fixup_arm_ldst_pcrel_12:
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// ARM PC-relative values are offset by 8.
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Value -= 4;
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// FALLTHROUGH
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case ARM::fixup_t2_ldst_pcrel_12: {
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// Offset by 4, adjusted by two due to the half-word ordering of thumb.
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Value -= 4;
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bool isAdd = true;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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assert ((Value < 4096) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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// Same addressing mode as fixup_arm_pcrel_10,
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// but with 16-bit halfwords swapped.
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if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
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uint64_t swapped = (Value & 0xFFFF0000) >> 16;
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swapped |= (Value & 0x0000FFFF) << 16;
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return swapped;
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}
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return Value;
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}
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case ARM::fixup_thumb_adr_pcrel_10:
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return ((Value - 4) >> 2) & 0xff;
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case ARM::fixup_arm_adr_pcrel_12: {
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// ARM PC-relative values are offset by 8.
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Value -= 8;
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unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
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if ((int64_t)Value < 0) {
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Value = -Value;
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opc = 2; // 0b0010
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}
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assert(ARM_AM::getSOImmVal(Value) != -1 &&
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"Out of range pc-relative fixup value!");
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// Encode the immediate and shift the opcode into place.
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return ARM_AM::getSOImmVal(Value) | (opc << 21);
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}
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case ARM::fixup_t2_adr_pcrel_12: {
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Value -= 4;
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unsigned opc = 0;
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if ((int64_t)Value < 0) {
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Value = -Value;
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opc = 5;
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}
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uint32_t out = (opc << 21);
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out |= (Value & 0x800) << 15;
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out |= (Value & 0x700) << 4;
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out |= (Value & 0x0FF);
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uint64_t swapped = (out & 0xFFFF0000) >> 16;
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swapped |= (out & 0x0000FFFF) << 16;
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return swapped;
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}
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case ARM::fixup_arm_condbranch:
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case ARM::fixup_arm_uncondbranch:
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// These values don't encode the low two bits since they're always zero.
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// Offset by 8 just as above.
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return 0xffffff & ((Value - 8) >> 2);
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case ARM::fixup_t2_uncondbranch: {
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Value = Value - 4;
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Value >>= 1; // Low bit is not encoded.
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uint32_t out = 0;
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bool I = Value & 0x800000;
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bool J1 = Value & 0x400000;
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bool J2 = Value & 0x200000;
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J1 ^= I;
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J2 ^= I;
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out |= I << 26; // S bit
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out |= !J1 << 13; // J1 bit
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out |= !J2 << 11; // J2 bit
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out |= (Value & 0x1FF800) << 5; // imm6 field
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out |= (Value & 0x0007FF); // imm11 field
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uint64_t swapped = (out & 0xFFFF0000) >> 16;
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swapped |= (out & 0x0000FFFF) << 16;
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return swapped;
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}
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case ARM::fixup_t2_condbranch: {
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Value = Value - 4;
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Value >>= 1; // Low bit is not encoded.
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uint64_t out = 0;
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out |= (Value & 0x80000) << 7; // S bit
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out |= (Value & 0x40000) >> 7; // J2 bit
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out |= (Value & 0x20000) >> 4; // J1 bit
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out |= (Value & 0x1F800) << 5; // imm6 field
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out |= (Value & 0x007FF); // imm11 field
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uint32_t swapped = (out & 0xFFFF0000) >> 16;
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swapped |= (out & 0x0000FFFF) << 16;
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return swapped;
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}
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case ARM::fixup_arm_thumb_bl: {
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// The value doesn't encode the low bit (always zero) and is offset by
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// four. The value is encoded into disjoint bit positions in the destination
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// opcode. x = unchanged, I = immediate value bit, S = sign extension bit
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//
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// BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
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//
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// Note that the halfwords are stored high first, low second; so we need
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// to transpose the fixup value here to map properly.
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unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
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uint32_t Binary = 0;
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Value = 0x3fffff & ((Value - 4) >> 1);
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Binary = (Value & 0x7ff) << 16; // Low imm11 value.
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Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
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Binary |= isNeg << 10; // Sign bit.
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return Binary;
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}
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case ARM::fixup_arm_thumb_blx: {
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// The value doesn't encode the low two bits (always zero) and is offset by
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// four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
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// positions in the destination opcode. x = unchanged, I = immediate value
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// bit, S = sign extension bit, 0 = zero.
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//
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// BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
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//
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// Note that the halfwords are stored high first, low second; so we need
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// to transpose the fixup value here to map properly.
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unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
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uint32_t Binary = 0;
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Value = 0xfffff & ((Value - 2) >> 2);
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Binary = (Value & 0x3ff) << 17; // Low imm10L value.
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Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
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Binary |= isNeg << 10; // Sign bit.
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return Binary;
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}
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case ARM::fixup_arm_thumb_cp:
|
|
// Offset by 4, and don't encode the low two bits. Two bytes of that
|
|
// 'off by 4' is implicitly handled by the half-word ordering of the
|
|
// Thumb encoding, so we only need to adjust by 2 here.
|
|
return ((Value - 2) >> 2) & 0xff;
|
|
case ARM::fixup_arm_thumb_cb: {
|
|
// Offset by 4 and don't encode the lower bit, which is always 0.
|
|
uint32_t Binary = (Value - 4) >> 1;
|
|
return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
|
|
}
|
|
case ARM::fixup_arm_thumb_br:
|
|
// Offset by 4 and don't encode the lower bit, which is always 0.
|
|
return ((Value - 4) >> 1) & 0x7ff;
|
|
case ARM::fixup_arm_thumb_bcc:
|
|
// Offset by 4 and don't encode the lower bit, which is always 0.
|
|
return ((Value - 4) >> 1) & 0xff;
|
|
case ARM::fixup_arm_pcrel_10_unscaled: {
|
|
Value = Value - 8; // ARM fixups offset by an additional word and don't
|
|
// need to adjust for the half-word ordering.
|
|
bool isAdd = true;
|
|
if ((int64_t)Value < 0) {
|
|
Value = -Value;
|
|
isAdd = false;
|
|
}
|
|
assert ((Value < 256) && "Out of range pc-relative fixup value!");
|
|
return Value | (isAdd << 23);
|
|
}
|
|
case ARM::fixup_arm_pcrel_10:
|
|
Value = Value - 4; // ARM fixups offset by an additional word and don't
|
|
// need to adjust for the half-word ordering.
|
|
// Fall through.
|
|
case ARM::fixup_t2_pcrel_10: {
|
|
// Offset by 4, adjusted by two due to the half-word ordering of thumb.
|
|
Value = Value - 4;
|
|
bool isAdd = true;
|
|
if ((int64_t)Value < 0) {
|
|
Value = -Value;
|
|
isAdd = false;
|
|
}
|
|
// These values don't encode the low two bits since they're always zero.
|
|
Value >>= 2;
|
|
assert ((Value < 256) && "Out of range pc-relative fixup value!");
|
|
Value |= isAdd << 23;
|
|
|
|
// Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
|
|
// swapped.
|
|
if (Kind == ARM::fixup_t2_pcrel_10) {
|
|
uint32_t swapped = (Value & 0xFFFF0000) >> 16;
|
|
swapped |= (Value & 0x0000FFFF) << 16;
|
|
return swapped;
|
|
}
|
|
|
|
return Value;
|
|
}
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
|
|
// FIXME: This should be in a separate file.
|
|
// ELF is an ELF of course...
|
|
class ELFARMAsmBackend : public ARMAsmBackend {
|
|
public:
|
|
uint8_t OSABI;
|
|
ELFARMAsmBackend(const Target &T, const StringRef TT,
|
|
uint8_t _OSABI)
|
|
: ARMAsmBackend(T, TT), OSABI(_OSABI) { }
|
|
|
|
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
|
|
uint64_t Value) const;
|
|
|
|
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
|
|
return createARMELFObjectWriter(OS, OSABI);
|
|
}
|
|
};
|
|
|
|
// FIXME: Raise this to share code between Darwin and ELF.
|
|
void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
|
|
unsigned DataSize, uint64_t Value) const {
|
|
unsigned NumBytes = 4; // FIXME: 2 for Thumb
|
|
Value = adjustFixupValue(Fixup.getKind(), Value);
|
|
if (!Value) return; // Doesn't change encoding.
|
|
|
|
unsigned Offset = Fixup.getOffset();
|
|
|
|
// For each byte of the fragment that the fixup touches, mask in the bits from
|
|
// the fixup value. The Value has been "split up" into the appropriate
|
|
// bitfields above.
|
|
for (unsigned i = 0; i != NumBytes; ++i)
|
|
Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
|
|
}
|
|
|
|
// FIXME: This should be in a separate file.
|
|
class DarwinARMAsmBackend : public ARMAsmBackend {
|
|
public:
|
|
const object::mach::CPUSubtypeARM Subtype;
|
|
DarwinARMAsmBackend(const Target &T, const StringRef TT,
|
|
object::mach::CPUSubtypeARM st)
|
|
: ARMAsmBackend(T, TT), Subtype(st) { }
|
|
|
|
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
|
|
return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
|
|
object::mach::CTM_ARM,
|
|
Subtype);
|
|
}
|
|
|
|
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
|
|
uint64_t Value) const;
|
|
|
|
virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
|
|
return false;
|
|
}
|
|
};
|
|
|
|
/// getFixupKindNumBytes - The number of bytes the fixup may change.
|
|
static unsigned getFixupKindNumBytes(unsigned Kind) {
|
|
switch (Kind) {
|
|
default:
|
|
llvm_unreachable("Unknown fixup kind!");
|
|
|
|
case FK_Data_1:
|
|
case ARM::fixup_arm_thumb_bcc:
|
|
case ARM::fixup_arm_thumb_cp:
|
|
case ARM::fixup_thumb_adr_pcrel_10:
|
|
return 1;
|
|
|
|
case FK_Data_2:
|
|
case ARM::fixup_arm_thumb_br:
|
|
case ARM::fixup_arm_thumb_cb:
|
|
return 2;
|
|
|
|
case ARM::fixup_arm_pcrel_10_unscaled:
|
|
case ARM::fixup_arm_ldst_pcrel_12:
|
|
case ARM::fixup_arm_pcrel_10:
|
|
case ARM::fixup_arm_adr_pcrel_12:
|
|
case ARM::fixup_arm_condbranch:
|
|
case ARM::fixup_arm_uncondbranch:
|
|
return 3;
|
|
|
|
case FK_Data_4:
|
|
case ARM::fixup_t2_ldst_pcrel_12:
|
|
case ARM::fixup_t2_condbranch:
|
|
case ARM::fixup_t2_uncondbranch:
|
|
case ARM::fixup_t2_pcrel_10:
|
|
case ARM::fixup_t2_adr_pcrel_12:
|
|
case ARM::fixup_arm_thumb_bl:
|
|
case ARM::fixup_arm_thumb_blx:
|
|
case ARM::fixup_arm_movt_hi16:
|
|
case ARM::fixup_arm_movw_lo16:
|
|
case ARM::fixup_arm_movt_hi16_pcrel:
|
|
case ARM::fixup_arm_movw_lo16_pcrel:
|
|
case ARM::fixup_t2_movt_hi16:
|
|
case ARM::fixup_t2_movw_lo16:
|
|
case ARM::fixup_t2_movt_hi16_pcrel:
|
|
case ARM::fixup_t2_movw_lo16_pcrel:
|
|
return 4;
|
|
}
|
|
}
|
|
|
|
void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
|
|
unsigned DataSize, uint64_t Value) const {
|
|
unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
|
|
Value = adjustFixupValue(Fixup.getKind(), Value);
|
|
if (!Value) return; // Doesn't change encoding.
|
|
|
|
unsigned Offset = Fixup.getOffset();
|
|
assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
|
|
|
|
// For each byte of the fragment that the fixup touches, mask in the
|
|
// bits from the fixup value.
|
|
for (unsigned i = 0; i != NumBytes; ++i)
|
|
Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
|
|
}
|
|
|
|
} // end anonymous namespace
|
|
|
|
MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
|
|
Triple TheTriple(TT);
|
|
|
|
if (TheTriple.isOSDarwin()) {
|
|
if (TheTriple.getArchName() == "armv4t" ||
|
|
TheTriple.getArchName() == "thumbv4t")
|
|
return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
|
|
else if (TheTriple.getArchName() == "armv5e" ||
|
|
TheTriple.getArchName() == "thumbv5e")
|
|
return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
|
|
else if (TheTriple.getArchName() == "armv6" ||
|
|
TheTriple.getArchName() == "thumbv6")
|
|
return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
|
|
return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
|
|
}
|
|
|
|
if (TheTriple.isOSWindows())
|
|
assert(0 && "Windows not supported on ARM");
|
|
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
|
|
return new ELFARMAsmBackend(T, TT, OSABI);
|
|
}
|