mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-31 12:30:06 +00:00
861e105e61
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228019 91177308-0d34-0410-b5e6-96231b3b80d8
352 lines
9.3 KiB
LLVM
352 lines
9.3 KiB
LLVM
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED
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; Compare byte
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declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32)
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define i32 @A4_cmpbgt(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmpb.gt(r0, r1)
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declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32)
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define i32 @A4_cmpbeq(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmpb.eq(r0, r1)
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declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32)
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define i32 @A4_cmpbgtu(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmpb.gtu(r0, r1)
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declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32)
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define i32 @A4_cmpbgti(i32 %a) {
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%z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = cmpb.gt(r0, #0)
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declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32)
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define i32 @A4_cmpbeqi(i32 %a) {
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%z = call i32 @llvm.hexagon.A4.cmpbeqi(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = cmpb.eq(r0, #0)
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declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32)
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define i32 @A4_cmpbgtui(i32 %a) {
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%z = call i32 @llvm.hexagon.A4.cmpbgtui(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = cmpb.gtu(r0, #0)
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; Compare half
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declare i32 @llvm.hexagon.A4.cmphgt(i32, i32)
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define i32 @A4_cmphgt(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.cmphgt(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmph.gt(r0, r1)
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declare i32 @llvm.hexagon.A4.cmpheq(i32, i32)
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define i32 @A4_cmpheq(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.cmpheq(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmph.eq(r0, r1)
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declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32)
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define i32 @A4_cmphgtu(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.cmphgtu(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmph.gtu(r0, r1)
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declare i32 @llvm.hexagon.A4.cmphgti(i32, i32)
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define i32 @A4_cmphgti(i32 %a) {
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%z = call i32 @llvm.hexagon.A4.cmphgti(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = cmph.gt(r0, #0)
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declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32)
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define i32 @A4_cmpheqi(i32 %a) {
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%z = call i32 @llvm.hexagon.A4.cmpheqi(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = cmph.eq(r0, #0)
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declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32)
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define i32 @A4_cmphgtui(i32 %a) {
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%z = call i32 @llvm.hexagon.A4.cmphgtui(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = cmph.gtu(r0, #0)
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; Compare doublewords
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declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64)
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define i32 @C2_cmpgtp(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.C2.cmpgtp(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmp.gt(r1:0, r3:2)
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declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64)
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define i32 @C2_cmpeqp(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.C2.cmpeqp(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmp.eq(r1:0, r3:2)
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declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64)
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define i32 @C2_cmpgtup(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.C2.cmpgtup(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = cmp.gtu(r1:0, r3:2)
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; Compare bitmask
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declare i32 @llvm.hexagon.C2.bitsclri(i32, i32)
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define i32 @C2_bitsclri(i32 %a) {
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%z = call i32 @llvm.hexagon.C2.bitsclri(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = bitsclr(r0, #0)
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declare i32 @llvm.hexagon.C4.nbitsclri(i32, i32)
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define i32 @C4_nbitsclri(i32 %a) {
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%z = call i32 @llvm.hexagon.C4.nbitsclri(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = !bitsclr(r0, #0)
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declare i32 @llvm.hexagon.C2.bitsset(i32, i32)
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define i32 @C2_bitsset(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C2.bitsset(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = bitsset(r0, r1)
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declare i32 @llvm.hexagon.C4.nbitsset(i32, i32)
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define i32 @C4_nbitsset(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C4.nbitsset(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = !bitsset(r0, r1)
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declare i32 @llvm.hexagon.C2.bitsclr(i32, i32)
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define i32 @C2_bitsclr(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C2.bitsclr(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = bitsclr(r0, r1)
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declare i32 @llvm.hexagon.C4.nbitsclr(i32, i32)
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define i32 @C4_nbitsclr(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C4.nbitsclr(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = !bitsclr(r0, r1)
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; Mask generate from predicate
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declare i64 @llvm.hexagon.C2.mask(i32)
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define i64 @C2_mask(i32 %a) {
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%z = call i64 @llvm.hexagon.C2.mask(i32 %a)
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ret i64 %z
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}
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; CHECK: = mask(p0)
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; Check for TLB match
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declare i32 @llvm.hexagon.A4.tlbmatch(i64, i32)
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define i32 @A4_tlbmatch(i64 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.tlbmatch(i64 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = tlbmatch(r1:0, r2)
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; Test bit
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declare i32 @llvm.hexagon.S2.tstbit.i(i32, i32)
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define i32 @S2_tstbit_i(i32 %a) {
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%z = call i32 @llvm.hexagon.S2.tstbit.i(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = tstbit(r0, #0)
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declare i32 @llvm.hexagon.S4.ntstbit.i(i32, i32)
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define i32 @S4_ntstbit_i(i32 %a) {
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%z = call i32 @llvm.hexagon.S4.ntstbit.i(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = !tstbit(r0, #0)
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declare i32 @llvm.hexagon.S2.tstbit.r(i32, i32)
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define i32 @S2_tstbit_r(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.S2.tstbit.r(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = tstbit(r0, r1)
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declare i32 @llvm.hexagon.S4.ntstbit.r(i32, i32)
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define i32 @S4_ntstbit_r(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.S4.ntstbit.r(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: p0 = !tstbit(r0, r1)
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; Vector compare halfwords
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declare i32 @llvm.hexagon.A2.vcmpheq(i64, i64)
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define i32 @A2_vcmpheq(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpheq(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.eq(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmphgt(i64, i64)
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define i32 @A2_vcmphgt(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmphgt(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gt(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmphgtu(i64, i64)
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define i32 @A2_vcmphgtu(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmphgtu(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gtu(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpheqi(i64, i32)
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define i32 @A4_vcmpheqi(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpheqi(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.eq(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmphgti(i64, i32)
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define i32 @A4_vcmphgti(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmphgti(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gt(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmphgtui(i64, i32)
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define i32 @A4_vcmphgtui(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmphgtui(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gtu(r1:0, #0)
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; Vector compare bytes for any match
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declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64)
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define i32 @A4_vcmpbeq_any(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = any8(vcmpb.eq(r1:0, r3:2))
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; Vector compare bytes
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declare i32 @llvm.hexagon.A2.vcmpbeq(i64, i64)
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define i32 @A2_vcmpbeq(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpbeq(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.eq(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64)
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define i32 @A2_vcmpbgtu(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gtu(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpbgt(i64, i64)
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define i32 @A4_vcmpbgt(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A4.vcmpbgt(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gt(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpbeqi(i64, i32)
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define i32 @A4_vcmpbeqi(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpbeqi(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.eq(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpbgti(i64, i32)
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define i32 @A4_vcmpbgti(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpbgti(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gt(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpbgtui(i64, i32)
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define i32 @A4_vcmpbgtui(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpbgtui(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gtu(r1:0, #0)
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; Vector compare words
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declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64)
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define i32 @A2_vcmpweq(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpweq(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.eq(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmpwgt(i64, i64)
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define i32 @A2_vcmpwgt(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpwgt(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gt(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64)
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define i32 @A2_vcmpwgtu(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpwgtu(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gtu(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpweqi(i64, i32)
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define i32 @A4_vcmpweqi(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpweqi(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.eq(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpwgti(i64, i32)
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define i32 @A4_vcmpwgti(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpwgti(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gt(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpwgtui(i64, i32)
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define i32 @A4_vcmpwgtui(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpwgtui(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gtu(r1:0, #0)
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; Viterbi pack even and odd predicate bitsclr
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declare i32 @llvm.hexagon.C2.vitpack(i32, i32)
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define i32 @C2_vitpack(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C2.vitpack(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = vitpack(p1, p0)
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; Vector mux
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declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64)
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define i64 @C2_vmux(i32 %a, i64 %b, i64 %c) {
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%z = call i64 @llvm.hexagon.C2.vmux(i32 %a, i64 %b, i64 %c)
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ret i64 %z
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}
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; CHECK: = vmux(p0, r3:2, r5:4)
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