mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-31 12:30:06 +00:00
18afdb3210
Summary: Code is mostly copied from AArch64 port and modified where needed for Mips. This handles the "non" legal cases of logical ops. Legal cases are handled by tablegen patterns. Test Plan: Make check test logopm.ll All of test-suite passes at O0/O2 and mips32 r1/r2 with this new change. Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231665 91177308-0d34-0410-b5e6-96231b3b80d8
606 lines
24 KiB
LLVM
606 lines
24 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
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@ub1 = common global i8 0, align 1
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@ub2 = common global i8 0, align 1
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@ub3 = common global i8 0, align 1
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@uc1 = common global i8 0, align 1
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@uc2 = common global i8 0, align 1
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@uc3 = common global i8 0, align 1
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@us1 = common global i16 0, align 2
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@us2 = common global i16 0, align 2
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@us3 = common global i16 0, align 2
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@ub = common global i8 0, align 1
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@uc = common global i8 0, align 1
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@us = common global i16 0, align 2
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@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
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@ui = common global i32 0, align 4
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@ui1 = common global i32 0, align 4
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@ui2 = common global i32 0, align 4
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@ui3 = common global i32 0, align 4
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; Function Attrs: noinline nounwind
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define void @andUb() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1
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%1 = load i8, i8* @ub2, align 1
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%conv0 = trunc i8 %0 to i1
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%conv1 = trunc i8 %1 to i1
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%and0 = and i1 %conv1, %conv0
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%conv3 = zext i1 %and0 to i8
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store i8 %conv3, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent andUb
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
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; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @andUb0() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1, !tbaa !2
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%conv = trunc i8 %0 to i1
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%and = and i1 %conv, 0
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%conv1 = zext i1 %and to i8
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store i8 %conv1, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent andUb0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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; CHECK: .end andUb0
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @andUb1() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1, !tbaa !2
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%conv = trunc i8 %0 to i1
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%and = and i1 %conv, 1
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%conv1 = zext i1 %and to i8
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store i8 %conv1, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent andUb1
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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; CHECK: .end andUb1
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @orUb() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1
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%1 = load i8, i8* @ub2, align 1
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%conv0 = trunc i8 %0 to i1
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%conv1 = trunc i8 %1 to i1
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%or0 = or i1 %conv1, %conv0
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%conv3 = zext i1 %or0 to i8
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store i8 %conv3, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent orUb
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
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; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @orUb0() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1, !tbaa !2
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%conv = trunc i8 %0 to i1
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%or = or i1 %conv, 0
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%conv1 = zext i1 %or to i8
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store i8 %conv1, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent orUb0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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; CHECK: .end orUb0
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @orUb1() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1, !tbaa !2
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%conv = trunc i8 %0 to i1
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%or = or i1 %conv, 1
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%conv1 = zext i1 %or to i8
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store i8 %conv1, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent orUb1
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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; CHECK: .end orUb1
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @xorUb() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1
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%1 = load i8, i8* @ub2, align 1
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%conv0 = trunc i8 %0 to i1
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%conv1 = trunc i8 %1 to i1
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%xor0 = xor i1 %conv1, %conv0
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%conv3 = zext i1 %xor0 to i8
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store i8 %conv3, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent xorUb
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
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; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @xorUb0() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1, !tbaa !2
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%conv = trunc i8 %0 to i1
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%xor = xor i1 %conv, 0
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%conv1 = zext i1 %xor to i8
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store i8 %conv1, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent xorUb0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $zero
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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; CHECK: .end xorUb0
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @xorUb1() #0 {
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entry:
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%0 = load i8, i8* @ub1, align 1, !tbaa !2
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%conv = trunc i8 %0 to i1
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%xor = xor i1 %conv, 1
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%conv1 = zext i1 %xor to i8
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store i8 %conv1, i8* @ub, align 1, !tbaa !2
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; CHECK-LABEL: .ent xorUb1
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
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; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
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; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
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; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
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; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
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; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
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; CHECK: .end xorUb1
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @andUc() #0 {
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entry:
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%0 = load i8, i8* @uc1, align 1, !tbaa !2
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%1 = load i8, i8* @uc2, align 1, !tbaa !2
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%and3 = and i8 %1, %0
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store i8 %and3, i8* @uc, align 1, !tbaa !2
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; CHECK-LABEL: .ent andUc
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
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; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
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; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
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; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
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; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC2]], $[[UB1]]
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; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @andUc0() #0 {
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entry:
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%0 = load i8, i8* @uc1, align 1, !tbaa !2
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%and = and i8 %0, 67
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store i8 %and, i8* @uc, align 1, !tbaa !2
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; CHECK-LABEL: .ent andUc0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
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; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
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; CHECK-DAG: addiu $[[CONST_67:[0-9]+]], $zero, 67
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; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_67]]
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; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
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; CHECK: .end andUc0
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @andUc1() #0 {
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entry:
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%0 = load i8, i8* @uc1, align 1, !tbaa !2
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%and = and i8 %0, 167
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store i8 %and, i8* @uc, align 1, !tbaa !2
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; CHECK-LABEL: .ent andUc1
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
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; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
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; CHECK-DAG: addiu $[[CONST_Neg89:[0-9]+]], $zero, -89
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; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_Neg89]]
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; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
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; CHECK: .end andUc1
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @orUc() #0 {
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entry:
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%0 = load i8, i8* @uc1, align 1, !tbaa !2
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%1 = load i8, i8* @uc2, align 1, !tbaa !2
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%or3 = or i8 %1, %0
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store i8 %or3, i8* @uc, align 1, !tbaa !2
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; CHECK-LABEL: .ent orUc
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
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; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
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; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
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; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
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; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
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; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]
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; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
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; CHECK: .end orUc
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @orUc0() #0 {
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entry:
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%0 = load i8, i8* @uc1, align 1, !tbaa !2
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%or = or i8 %0, 69
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store i8 %or, i8* @uc, align 1, !tbaa !2
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; CHECK-LABEL: .ent orUc0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
|
|
; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_69:[0-9]+]], $zero, 69
|
|
; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_69]]
|
|
; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
|
|
; CHECK: .end orUc0
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @orUc1() #0 {
|
|
entry:
|
|
%0 = load i8, i8* @uc1, align 1, !tbaa !2
|
|
%or = or i8 %0, 238
|
|
store i8 %or, i8* @uc, align 1, !tbaa !2
|
|
; CHECK-LABEL: .ent orUc1
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
|
|
; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_neg18:[0-9]+]], $zero, -18
|
|
; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_neg18]]
|
|
; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
|
|
; CHECK: .end orUc1
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @xorUc() #0 {
|
|
entry:
|
|
%0 = load i8, i8* @uc1, align 1, !tbaa !2
|
|
%1 = load i8, i8* @uc2, align 1, !tbaa !2
|
|
%xor3 = xor i8 %1, %0
|
|
store i8 %xor3, i8* @uc, align 1, !tbaa !2
|
|
; CHECK-LABEL: .ent xorUc
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
|
|
; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
|
|
; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
|
|
; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]
|
|
; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
|
|
; CHECK: .end xorUc
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @xorUc0() #0 {
|
|
entry:
|
|
%0 = load i8, i8* @uc1, align 1, !tbaa !2
|
|
%xor = xor i8 %0, 23
|
|
store i8 %xor, i8* @uc, align 1, !tbaa !2
|
|
; CHECK-LABEL: .ent xorUc0
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
|
|
; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_23:[0-9]+]], $zero, 23
|
|
; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_23]]
|
|
; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
|
|
; CHECK: .end xorUc0
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @xorUc1() #0 {
|
|
entry:
|
|
%0 = load i8, i8* @uc1, align 1, !tbaa !2
|
|
%xor = xor i8 %0, 120
|
|
store i8 %xor, i8* @uc, align 1, !tbaa !2
|
|
; CHECK-LABEL: .ent xorUc1
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
|
|
; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_120:[0-9]+]], $zero, 120
|
|
; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_120]]
|
|
; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
|
|
; CHECK: .end xorUc1
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @andUs() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%1 = load i16, i16* @us2, align 2, !tbaa !5
|
|
%and3 = and i16 %1, %0
|
|
store i16 %and3, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent andUs
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
|
|
; CHECK-DAG: and $[[RES:[0-9]+]], $[[US2]], $[[UB1]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end andUs
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @andUs0() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%and = and i16 %0, 4660
|
|
store i16 %and, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent andUs0
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_4660:[0-9]+]], $zero, 4660
|
|
; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_4660]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end andUs0
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @andUs1() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%and = and i16 %0, 61351
|
|
store i16 %and, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent andUs1
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_Neg4185:[0-9]+]], $zero, -4185
|
|
; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg4185]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end andUs1
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @orUs() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%1 = load i16, i16* @us2, align 2, !tbaa !5
|
|
%or3 = or i16 %1, %0
|
|
store i16 %or3, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent orUs
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
|
|
; CHECK-DAG: or $[[RES:[0-9]+]], $[[US2]], $[[US1]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end orUs
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @orUs0() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%or = or i16 %0, 17666
|
|
store i16 %or, i16* @us, align 2, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @orUs1() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%or = or i16 %0, 60945
|
|
store i16 %or, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent orUs1
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_neg4591:[0-9]+]], $zero, -4591
|
|
; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_neg4591]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end orUs1
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @xorUs() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%1 = load i16, i16* @us2, align 2, !tbaa !5
|
|
%xor3 = xor i16 %1, %0
|
|
store i16 %xor3, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent xorUs
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
|
|
; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US2]], $[[US1]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end xorUs
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @xorUs0() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%xor = xor i16 %0, 6062
|
|
store i16 %xor, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent xorUs0
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_6062:[0-9]+]], $zero, 6062
|
|
; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_6062]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end xorUs0
|
|
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: noinline nounwind
|
|
define void @xorUs1() #0 {
|
|
entry:
|
|
%0 = load i16, i16* @us1, align 2, !tbaa !5
|
|
%xor = xor i16 %0, 60024
|
|
store i16 %xor, i16* @us, align 2, !tbaa !5
|
|
; CHECK-LABEL: .ent xorUs1
|
|
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
|
|
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
|
|
; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
|
|
; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
|
|
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
|
|
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
|
|
; CHECK-DAG: addiu $[[CONST_Neg5512:[0-9]+]], $zero, -5512
|
|
; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg5512]]
|
|
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
|
|
; CHECK: .end xorUs1
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
|
attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
|
attributes #2 = { nounwind }
|
|
|
|
!llvm.module.flags = !{!0}
|
|
!llvm.ident = !{!1}
|
|
|
|
!0 = !{i32 1, !"PIC Level", i32 2}
|
|
!1 = !{!"clang version 3.7.0 (trunk)"}
|
|
!2 = !{!3, !3, i64 0}
|
|
!3 = !{!"omnipotent char", !4, i64 0}
|
|
!4 = !{!"Simple C/C++ TBAA"}
|
|
!5 = !{!6, !6, i64 0}
|
|
!6 = !{!"short", !3, i64 0}
|