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https://github.com/c64scene-ar/llvm-6502.git
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26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
55 lines
2.1 KiB
LLVM
55 lines
2.1 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s -check-prefix=mips32r2
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s -check-prefix=mips32
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@f = common global float 0.000000e+00, align 4
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@de = common global double 0.000000e+00, align 8
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; Function Attrs: nounwind
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define void @f1() #0 {
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entry:
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store float 0x3FFA76C8C0000000, float* @f, align 4
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ret void
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; CHECK: .ent f1
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; CHECK: lui $[[REG1:[0-9]+]], 16339
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; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662
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; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
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; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
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; CHECK: swc1 $f[[REG3]], 0($[[REG4]])
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; CHECK: .end f1
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}
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; Function Attrs: nounwind
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define void @d1() #0 {
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entry:
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store double 1.234567e+00, double* @de, align 8
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; mip32r2: .ent d1
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; mips32r2: lui $[[REG1a:[0-9]+]], 16371
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; mips32r2: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
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; mips32r2: lui $[[REG1b:[0-9]+]], 21403
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; mips32r2: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
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; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
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; mips32r2: mthc1 $[[REG2a]], $f[[REG3]]
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; mips32r2: sdc1 $f[[REG3]], 0(${{[0-9]+}})
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; mips32r2: .end d1
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; mips32: .ent d1
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; mips32: lui $[[REG1a:[0-9]+]], 16371
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; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
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; mips32: lui $[[REG1b:[0-9]+]], 21403
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; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
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; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
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; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
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; mips32: sdc1 $f[[REG3]], 0(${{[0-9]+}})
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; mips32: .end d1
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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