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5ee24f37af
Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211012 91177308-0d34-0410-b5e6-96231b3b80d8
13 lines
638 B
ArmAsm
13 lines
638 B
ArmAsm
# Instructions that are available for the current ISA but should be rejected by
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# the assembler (e.g. invalid set of operands or operand's restrictions not met).
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1
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# RUN: FileCheck %s < %t1 -check-prefix=ASM
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.text
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.set noreorder
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.set noat
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jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
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jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
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ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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