mirror of
https://github.com/c64scene-ar/llvm-6502.git
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4d3b6131c7
Add test cases where we don't expect to trigger the combine optimizations introduced at revision 212748. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212756 91177308-0d34-0410-b5e6-96231b3b80d8
254 lines
7.8 KiB
LLVM
254 lines
7.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Check that DAGCombiner correctly folds the following pairs of shuffles
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; using the following rules:
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; 1. shuffle(shuffle(x, y), undef) -> x
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; 2. shuffle(shuffle(x, y), undef) -> y
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; 3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
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; 4. shuffle(shuffle(x, y), undef) -> shuffle(undef, y)
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;
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; Rules 3. and 4. are used only if the resulting shuffle mask is legal.
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define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test1
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; Mask: [3,0,0,1]
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; CHECK: pshufd $67
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; CHECK-NEXT: ret
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define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test2
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; Mask: [2,0,0,3]
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; CHECK: pshufd $-62
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; CHECK-NEXT: ret
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define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test3
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; Mask: [2,0,0,3]
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; CHECK: pshufd $-62
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; CHECK-NEXT: ret
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define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test4
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; Mask: [0,0,0,1]
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; CHECK: pshufd $64
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; CHECK-NEXT: ret
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define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test5
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; Mask: [1,1]
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; CHECK: movhlps
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; CHECK-NEXT: ret
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define <4 x i32> @test6(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test6
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; Mask: [2,0,0,0]
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; CHECK: pshufd $2
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; CHECK-NEXT: ret
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define <4 x i32> @test7(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test7
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; Mask: [0,2,0,2]
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; CHECK: pshufd $-120
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; CHECK-NEXT: ret
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define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test8
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; Mask: [1,0,3,0]
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; CHECK: pshufd $49
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; CHECK-NEXT: ret
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define <4 x i32> @test9(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test9
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; Mask: [1,3,0,2]
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; CHECK: pshufd $-115
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; CHECK-NEXT: ret
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define <4 x i32> @test10(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test10
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; Mask: [1,0,1,0]
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; CHECK: pshufd $17
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; CHECK-NEXT: ret
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define <4 x i32> @test11(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test11
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; Mask: [1,0,2,1]
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; CHECK: pshufd $97
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; CHECK-NEXT: ret
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define <4 x i32> @test12(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test12
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; Mask: [0,0,0,0]
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; CHECK: pshufd $0
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; CHECK-NEXT: ret
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; The following pair of shuffles is folded into vector %A.
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define <4 x i32> @test13(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: pshufd
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; CHECK: ret
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; The following pair of shuffles is folded into vector %B.
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define <4 x i32> @test14(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: pshufd
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; CHECK: ret
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; Verify that we don't optimize the following cases. We expect more than one shuffle.
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define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test15
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; CHECK: shufps $114
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test16
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; CHECK: blendps $10
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test17
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; CHECK: shufps $120
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test18(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test18
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; CHECK: blendps $11
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; CHECK-NEXT: pshufd $-59
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; CHECK-NEXT: ret
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define <4 x i32> @test19(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test19
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; CHECK: shufps $-104
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; CHECK-NEXT: pshufd $2
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; CHECK-NEXT: ret
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define <4 x i32> @test20(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test20
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; CHECK: shufps $11
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test21(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test21
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; CHECK: shufps $120
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; CHECK-NEXT: pshufd $-60
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; CHECK-NEXT: ret
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define <4 x i32> @test22(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test22
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; CHECK: blendps $11
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; CHECK-NEXT: pshufd $-43
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; CHECK-NEXT: ret
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