mirror of
https://github.com/c64scene-ar/llvm-6502.git
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aa5b9c0f6f
be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215154 91177308-0d34-0410-b5e6-96231b3b80d8
282 lines
9.7 KiB
C++
282 lines
9.7 KiB
C++
//===-- Sparc/SparcCodeEmitter.cpp - Convert Sparc Code to Machine Code ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===---------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the Sparc machine instructions
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// into relocatable machine code.
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//
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//===---------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "MCTargetDesc/SparcMCExpr.h"
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#include "SparcRelocations.h"
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#include "SparcTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "jit"
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class SparcCodeEmitter : public MachineFunctionPass {
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SparcJITInfo *JTI;
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const SparcInstrInfo *II;
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const DataLayout *TD;
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const SparcSubtarget *Subtarget;
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TargetMachine &TM;
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JITCodeEmitter &MCE;
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const std::vector<MachineConstantPoolEntry> *MCPEs;
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bool IsPIC;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineModuleInfo> ();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static char ID;
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public:
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SparcCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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: MachineFunctionPass(ID), JTI(nullptr), II(nullptr), TD(nullptr),
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TM(tm), MCE(mce), MCPEs(nullptr),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "Sparc Machine Code Emitter";
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}
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
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void emitInstruction(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB);
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private:
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const;
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unsigned getCallTargetOpValue(const MachineInstr &MI,
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unsigned) const;
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unsigned getBranchTargetOpValue(const MachineInstr &MI,
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unsigned) const;
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unsigned getBranchPredTargetOpValue(const MachineInstr &MI,
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unsigned) const;
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unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI,
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unsigned) const;
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void emitWord(unsigned Word);
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unsigned getRelocation(const MachineInstr &MI,
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const MachineOperand &MO) const;
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void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc) const;
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
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void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc) const;
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};
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} // end anonymous namespace.
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char SparcCodeEmitter::ID = 0;
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bool SparcCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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SparcTargetMachine &Target = static_cast<SparcTargetMachine &>(
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const_cast<TargetMachine &>(MF.getTarget()));
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JTI = Target.getSubtargetImpl()->getJITInfo();
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II = Target.getSubtargetImpl()->getInstrInfo();
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TD = Target.getSubtargetImpl()->getDataLayout();
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Subtarget = &TM.getSubtarget<SparcSubtarget>();
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MCPEs = &MF.getConstantPool()->getConstants();
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JTI->Initialize(MF, IsPIC);
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MCE.setModuleInfo(&getAnalysis<MachineModuleInfo> ());
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do {
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DEBUG(errs() << "JITTing function '"
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<< MF.getName() << "'\n");
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB){
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
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E = MBB->instr_end(); I != E;)
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emitInstruction(*I++, *MBB);
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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void SparcCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB) {
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DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI);
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MCE.processDebugLoc(MI->getDebugLoc(), true);
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++NumEmitted;
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switch (MI->getOpcode()) {
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default: {
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emitWord(getBinaryCodeForInstr(*MI));
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break;
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}
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case TargetOpcode::INLINEASM: {
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// We allow inline assembler nodes with empty bodies - they can
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// implicitly define registers, which is ok for JIT.
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if (MI->getOperand(0).getSymbolName()[0]) {
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report_fatal_error("JIT does not support inline asm!");
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}
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break;
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}
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case TargetOpcode::CFI_INSTRUCTION:
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break;
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case TargetOpcode::EH_LABEL: {
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MCE.emitLabel(MI->getOperand(0).getMCSymbol());
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break;
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}
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL: {
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// Do nothing.
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break;
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}
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case SP::GETPCX: {
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report_fatal_error("JIT does not support pseudo instruction GETPCX yet!");
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break;
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}
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}
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MCE.processDebugLoc(MI->getDebugLoc(), false);
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}
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void SparcCodeEmitter::emitWord(unsigned Word) {
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DEBUG(errs() << " 0x";
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errs().write_hex(Word) << "\n");
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MCE.emitWordBE(Word);
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const {
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if (MO.isReg())
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return TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(
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MO.getReg());
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else if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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else if (MO.isGlobal())
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emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO));
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else if (MO.isSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO));
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else if (MO.isCPI())
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emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO));
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else if (MO.isMBB())
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emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
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else
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llvm_unreachable("Unable to encode MachineOperand!");
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return 0;
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}
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unsigned SparcCodeEmitter::getCallTargetOpValue(const MachineInstr &MI,
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unsigned opIdx) const {
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const MachineOperand MO = MI.getOperand(opIdx);
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return getMachineOpValue(MI, MO);
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}
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unsigned SparcCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
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unsigned opIdx) const {
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const MachineOperand MO = MI.getOperand(opIdx);
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return getMachineOpValue(MI, MO);
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}
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unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI,
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unsigned opIdx) const {
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const MachineOperand MO = MI.getOperand(opIdx);
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return getMachineOpValue(MI, MO);
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}
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unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI,
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unsigned opIdx) const {
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const MachineOperand MO = MI.getOperand(opIdx);
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return getMachineOpValue(MI, MO);
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}
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unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,
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const MachineOperand &MO) const {
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unsigned TF = MO.getTargetFlags();
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switch (TF) {
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default:
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case SparcMCExpr::VK_Sparc_None: break;
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case SparcMCExpr::VK_Sparc_LO: return SP::reloc_sparc_lo;
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case SparcMCExpr::VK_Sparc_HI: return SP::reloc_sparc_hi;
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case SparcMCExpr::VK_Sparc_H44: return SP::reloc_sparc_h44;
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case SparcMCExpr::VK_Sparc_M44: return SP::reloc_sparc_m44;
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case SparcMCExpr::VK_Sparc_L44: return SP::reloc_sparc_l44;
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case SparcMCExpr::VK_Sparc_HH: return SP::reloc_sparc_hh;
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case SparcMCExpr::VK_Sparc_HM: return SP::reloc_sparc_hm;
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}
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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default: break;
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case SP::CALL: return SP::reloc_sparc_pc30;
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case SP::BA:
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case SP::BCOND:
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case SP::FBCOND: return SP::reloc_sparc_pc22;
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case SP::BPXCC: return SP::reloc_sparc_pc19;
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}
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llvm_unreachable("unknown reloc!");
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}
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void SparcCodeEmitter::emitGlobalAddress(const GlobalValue *GV,
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unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
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const_cast<GlobalValue *>(GV), 0,
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true));
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}
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void SparcCodeEmitter::
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emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES, 0, 0));
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}
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void SparcCodeEmitter::
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emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, 0, false));
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}
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void SparcCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
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unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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Reloc, BB));
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}
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/// createSparcJITCodeEmitterPass - Return a pass that emits the collected Sparc
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/// code to the specified MCE object.
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FunctionPass *llvm::createSparcJITCodeEmitterPass(SparcTargetMachine &TM,
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JITCodeEmitter &JCE) {
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return new SparcCodeEmitter(TM, JCE);
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}
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#include "SparcGenCodeEmitter.inc"
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