mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-19 17:33:29 +00:00
f6a4d3c2f3
Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
737 B
LLVM
28 lines
737 B
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
|
|
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
|
|
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
|
|
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
|
|
|
|
define float @test(float %a, float %b) {
|
|
entry:
|
|
%dum = fadd float %a, %b
|
|
%0 = tail call float @fabsf(float %dum)
|
|
%dum1 = fadd float %0, %b
|
|
ret float %dum1
|
|
}
|
|
|
|
declare float @fabsf(float)
|
|
|
|
; VFP2: test:
|
|
; VFP2: vabs.f32 s1, s1
|
|
|
|
; NFP1: test:
|
|
; NFP1: vabs.f32 d1, d1
|
|
; NFP0: test:
|
|
; NFP0: vabs.f32 s1, s1
|
|
|
|
; CORTEXA8: test:
|
|
; CORTEXA8: vabs.f32 d1, d1
|
|
; CORTEXA9: test:
|
|
; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
|