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2d28617de2
better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
357 lines
11 KiB
C++
357 lines
11 KiB
C++
//===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Cell implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "SPU.h"
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#include "SPURegisterInfo.h"
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#include "SPUInstrBuilder.h"
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#include "SPUSubtarget.h"
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#include "SPUMachineFunction.h"
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#include "SPUFrameLowering.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#define GET_REGINFO_TARGET_DESC
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#include "SPUGenRegisterInfo.inc"
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using namespace llvm;
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// PPC::F14, return the number that it corresponds to (e.g. 14).
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unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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using namespace SPU;
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switch (RegEnum) {
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case SPU::R0: return 0;
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case SPU::R1: return 1;
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case SPU::R2: return 2;
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case SPU::R3: return 3;
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case SPU::R4: return 4;
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case SPU::R5: return 5;
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case SPU::R6: return 6;
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case SPU::R7: return 7;
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case SPU::R8: return 8;
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case SPU::R9: return 9;
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case SPU::R10: return 10;
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case SPU::R11: return 11;
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case SPU::R12: return 12;
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case SPU::R13: return 13;
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case SPU::R14: return 14;
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case SPU::R15: return 15;
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case SPU::R16: return 16;
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case SPU::R17: return 17;
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case SPU::R18: return 18;
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case SPU::R19: return 19;
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case SPU::R20: return 20;
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case SPU::R21: return 21;
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case SPU::R22: return 22;
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case SPU::R23: return 23;
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case SPU::R24: return 24;
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case SPU::R25: return 25;
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case SPU::R26: return 26;
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case SPU::R27: return 27;
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case SPU::R28: return 28;
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case SPU::R29: return 29;
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case SPU::R30: return 30;
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case SPU::R31: return 31;
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case SPU::R32: return 32;
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case SPU::R33: return 33;
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case SPU::R34: return 34;
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case SPU::R35: return 35;
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case SPU::R36: return 36;
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case SPU::R37: return 37;
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case SPU::R38: return 38;
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case SPU::R39: return 39;
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case SPU::R40: return 40;
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case SPU::R41: return 41;
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case SPU::R42: return 42;
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case SPU::R43: return 43;
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case SPU::R44: return 44;
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case SPU::R45: return 45;
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case SPU::R46: return 46;
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case SPU::R47: return 47;
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case SPU::R48: return 48;
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case SPU::R49: return 49;
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case SPU::R50: return 50;
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case SPU::R51: return 51;
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case SPU::R52: return 52;
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case SPU::R53: return 53;
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case SPU::R54: return 54;
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case SPU::R55: return 55;
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case SPU::R56: return 56;
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case SPU::R57: return 57;
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case SPU::R58: return 58;
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case SPU::R59: return 59;
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case SPU::R60: return 60;
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case SPU::R61: return 61;
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case SPU::R62: return 62;
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case SPU::R63: return 63;
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case SPU::R64: return 64;
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case SPU::R65: return 65;
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case SPU::R66: return 66;
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case SPU::R67: return 67;
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case SPU::R68: return 68;
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case SPU::R69: return 69;
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case SPU::R70: return 70;
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case SPU::R71: return 71;
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case SPU::R72: return 72;
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case SPU::R73: return 73;
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case SPU::R74: return 74;
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case SPU::R75: return 75;
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case SPU::R76: return 76;
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case SPU::R77: return 77;
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case SPU::R78: return 78;
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case SPU::R79: return 79;
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case SPU::R80: return 80;
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case SPU::R81: return 81;
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case SPU::R82: return 82;
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case SPU::R83: return 83;
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case SPU::R84: return 84;
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case SPU::R85: return 85;
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case SPU::R86: return 86;
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case SPU::R87: return 87;
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case SPU::R88: return 88;
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case SPU::R89: return 89;
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case SPU::R90: return 90;
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case SPU::R91: return 91;
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case SPU::R92: return 92;
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case SPU::R93: return 93;
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case SPU::R94: return 94;
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case SPU::R95: return 95;
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case SPU::R96: return 96;
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case SPU::R97: return 97;
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case SPU::R98: return 98;
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case SPU::R99: return 99;
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case SPU::R100: return 100;
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case SPU::R101: return 101;
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case SPU::R102: return 102;
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case SPU::R103: return 103;
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case SPU::R104: return 104;
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case SPU::R105: return 105;
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case SPU::R106: return 106;
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case SPU::R107: return 107;
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case SPU::R108: return 108;
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case SPU::R109: return 109;
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case SPU::R110: return 110;
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case SPU::R111: return 111;
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case SPU::R112: return 112;
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case SPU::R113: return 113;
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case SPU::R114: return 114;
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case SPU::R115: return 115;
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case SPU::R116: return 116;
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case SPU::R117: return 117;
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case SPU::R118: return 118;
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case SPU::R119: return 119;
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case SPU::R120: return 120;
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case SPU::R121: return 121;
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case SPU::R122: return 122;
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case SPU::R123: return 123;
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case SPU::R124: return 124;
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case SPU::R125: return 125;
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case SPU::R126: return 126;
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case SPU::R127: return 127;
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default:
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report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
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}
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}
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SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
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const TargetInstrInfo &tii) :
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SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii)
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{
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
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return &SPU::R32CRegClass;
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}
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const unsigned *
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SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
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{
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// Cell ABI calling convention
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static const unsigned SPU_CalleeSaveRegs[] = {
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SPU::R80, SPU::R81, SPU::R82, SPU::R83,
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SPU::R84, SPU::R85, SPU::R86, SPU::R87,
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SPU::R88, SPU::R89, SPU::R90, SPU::R91,
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SPU::R92, SPU::R93, SPU::R94, SPU::R95,
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SPU::R96, SPU::R97, SPU::R98, SPU::R99,
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SPU::R100, SPU::R101, SPU::R102, SPU::R103,
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SPU::R104, SPU::R105, SPU::R106, SPU::R107,
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SPU::R108, SPU::R109, SPU::R110, SPU::R111,
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SPU::R112, SPU::R113, SPU::R114, SPU::R115,
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SPU::R116, SPU::R117, SPU::R118, SPU::R119,
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SPU::R120, SPU::R121, SPU::R122, SPU::R123,
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SPU::R124, SPU::R125, SPU::R126, SPU::R127,
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SPU::R2, /* environment pointer */
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SPU::R1, /* stack pointer */
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SPU::R0, /* link register */
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0 /* end */
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};
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return SPU_CalleeSaveRegs;
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}
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/*!
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R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
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generally unused) are the Cell's reserved registers
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*/
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BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(SPU::R0); // LR
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Reserved.set(SPU::R1); // SP
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Reserved.set(SPU::R2); // environment pointer
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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//--------------------------------------------------------------------------
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void
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SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I)
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const
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{
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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void
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SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const
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{
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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DebugLoc dl = II->getDebugLoc();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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MachineOperand &SPOp = MI.getOperand(i);
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int FrameIndex = SPOp.getIndex();
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// Now add the frame object offset to the offset from r1.
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int Offset = MFI->getObjectOffset(FrameIndex);
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// Most instructions, except for generated FrameIndex additions using AIr32
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// and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the
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// immediate in operand 2.
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unsigned OpNo = 1;
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if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
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OpNo = 2;
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MachineOperand &MO = MI.getOperand(OpNo);
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// Offset is biased by $lr's slot at the bottom.
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Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize();
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assert((Offset & 0xf) == 0
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&& "16-byte alignment violated in eliminateFrameIndex");
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// Replace the FrameIndex with base register with $sp (aka $r1)
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SPOp.ChangeToRegister(SPU::R1, false);
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// if 'Offset' doesn't fit to the D-form instruction's
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// immediate, convert the instruction to X-form
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// if the instruction is not an AI (which takes a s10 immediate), assume
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// it is a load/store that can take a s14 immediate
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if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
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|| !isInt<14>(Offset)) {
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int newOpcode = convertDFormToXForm(MI.getOpcode());
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unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
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BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
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.addImm(Offset);
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BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
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.addReg(tmpReg, RegState::Kill)
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.addReg(SPU::R1);
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// remove the replaced D-form instruction
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MBB.erase(II);
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} else {
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MO.ChangeToImmediate(Offset);
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}
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}
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unsigned
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SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
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{
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return SPU::R1;
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}
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int
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SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
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{
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switch(dFormOpcode)
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{
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case SPU::AIr32: return SPU::Ar32;
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case SPU::LQDr32: return SPU::LQXr32;
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case SPU::LQDr128: return SPU::LQXr128;
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case SPU::LQDv16i8: return SPU::LQXv16i8;
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case SPU::LQDv4i32: return SPU::LQXv4i32;
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case SPU::LQDv4f32: return SPU::LQXv4f32;
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case SPU::STQDr32: return SPU::STQXr32;
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case SPU::STQDr128: return SPU::STQXr128;
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case SPU::STQDv16i8: return SPU::STQXv16i8;
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case SPU::STQDv4i32: return SPU::STQXv4i32;
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case SPU::STQDv4f32: return SPU::STQXv4f32;
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default: assert( false && "Unhandled D to X-form conversion");
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}
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// default will assert, but need to return something to keep the
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// compiler happy.
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return dFormOpcode;
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}
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// TODO this is already copied from PPC. Could this convenience function
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// be moved to the RegScavenger class?
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unsigned
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SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
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RegScavenger *RS,
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const TargetRegisterClass *RC,
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int SPAdj) const
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{
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assert(RS && "Register scavenging must be on");
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unsigned Reg = RS->FindUnusedReg(RC);
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if (Reg == 0)
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Reg = RS->scavengeRegister(RC, II, SPAdj);
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assert( Reg && "Register scavenger failed");
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return Reg;
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}
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