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07a73755d3
that have a frame pointer. This change fixes Burg. In addition, make the necessary changes to floating point code gen and constant loading after Chris Lattner's fixes to the asm writer. These changes fix MallocBench/gs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15873 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.4 KiB
TableGen
41 lines
1.4 KiB
TableGen
//===- PPC32RegisterInfo.td - The PowerPC32 Register File --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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include "PowerPCRegisterInfo.td"
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/// Register classes
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// Allocate volatiles first
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// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
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def GPRC : RegisterClass<i32, 8,
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[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
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R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
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R16, R15, R14, R13, R31, R0, R1, LR]>
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{
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let Methods = [{
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iterator allocation_order_begin(MachineFunction &MF) const {
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return begin() + (AIX ? 1 : 0);
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}
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iterator allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF))
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return end()-4;
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else
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return end()-3;
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}
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}];
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}
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def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
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F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
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