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https://github.com/c64scene-ar/llvm-6502.git
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d30a98e43a
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
521 B
LLVM
23 lines
521 B
LLVM
; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=V6
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; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5
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; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI
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; rdar://r6949835
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@b = external global i64*
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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;V6: ldrd r2, [r2]
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;V5: ldr r3, [r2]
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;V5: ldr r2, [r2, #4]
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;EABI: ldr r3, [r2]
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;EABI: ldr r2, [r2, #4]
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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%2 = mul i64 %1, %a
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ret i64 %2
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}
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