6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity
d32974f9dc
llvm-6502/test/MC/AArch64/arm64-elf-relocs.s
Will Newton 87a2f3751c Update AArch64 ELF relocations to ABI 1.0 
This mostly entails adding relocations, however there are a couple of
changes to existing relocations:

1. R_AARCH64_NONE is defined to be zero rather than 256

R_AARCH64_NONE has been defined to be zero for a long time elsewhere
e.g. binutils and glibc since the submission of the AArch64 port in
2012 so this is required for compatibility.

2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21

I don't think there is any way for relocation names to leak out of LLVM
so this should not break anything.

Tested with check-all with no regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 10:49:18 +00:00

250 lines
8.7 KiB
ArmAsm
Raw Blame History

// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
add x0, x2, #:lo12:sym
// CHECK: add x0, x2, :lo12:sym
// CHECK-OBJ: 0 R_AARCH64_ADD_ABS_LO12_NC sym
add x5, x7, #:dtprel_lo12:sym
// CHECK: add x5, x7, :dtprel_lo12:sym
// CHECK-OBJ: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
add x9, x12, #:dtprel_lo12_nc:sym
// CHECK: add x9, x12, :dtprel_lo12_nc:sym
// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
add x20, x30, #:tprel_lo12:sym
// CHECK: add x20, x30, :tprel_lo12:sym
// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
add x9, x12, #:tprel_lo12_nc:sym
// CHECK: add x9, x12, :tprel_lo12_nc:sym
// CHECK-OBJ: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
add x5, x0, #:tlsdesc_lo12:sym
// CHECK: add x5, x0, :tlsdesc_lo12:sym
// CHECK-OBJ: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
add x0, x2, #:lo12:sym+8
// CHECK: add x0, x2, :lo12:sym
// CHECK-OBJ: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
add x5, x7, #:dtprel_lo12:sym+1
// CHECK: add x5, x7, :dtprel_lo12:sym+1
// CHECK-OBJ: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
add x9, x12, #:dtprel_lo12_nc:sym+2
// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
add x20, x30, #:tprel_lo12:sym+12
// CHECK: add x20, x30, :tprel_lo12:sym+12
// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
add x9, x12, #:tprel_lo12_nc:sym+54
// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
// CHECK-OBJ: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
add x5, x0, #:tlsdesc_lo12:sym+70
// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
// CHECK-OBJ: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
.hword sym + 4 - .
// CHECK-OBJ: 30 R_AARCH64_PREL16 sym+4
.word sym - . + 8
// CHECK-OBJ: 32 R_AARCH64_PREL32 sym+8
.xword sym-.
// CHECK-OBJ: 36 R_AARCH64_PREL64 sym{{$}}
.hword sym
// CHECK-OBJ: 3e R_AARCH64_ABS16 sym
.word sym+1
// CHECK-OBJ: 40 R_AARCH64_ABS32 sym+1
.xword sym+16
// CHECK-OBJ: 44 R_AARCH64_ABS64 sym+16
adrp x0, sym
// CHECK: adrp x0, sym
// CHECK-OBJ: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
adrp x15, :got:sym
// CHECK: adrp x15, :got:sym
// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
adrp x29, :gottprel:sym
// CHECK: adrp x29, :gottprel:sym
// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
adrp x2, :tlsdesc:sym
// CHECK: adrp x2, :tlsdesc:sym
// CHECK-OBJ: 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
// LLVM is not competent enough to do this relocation because the
// page boundary could occur anywhere after linking. A relocation
// is needed.
adrp x3, trickQuestion
.global trickQuestion
trickQuestion:
// CHECK: adrp x3, trickQuestion
// CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
ldrb w2, [x3, :lo12:sym]
ldrsb w5, [x7, #:lo12:sym]
ldrsb x11, [x13, :lo12:sym]
ldr b17, [x19, #:lo12:sym]
// CHECK: ldrb w2, [x3, :lo12:sym]
// CHECK: ldrsb w5, [x7, :lo12:sym]
// CHECK: ldrsb x11, [x13, :lo12:sym]
// CHECK: ldr b17, [x19, :lo12:sym]
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
ldrb w23, [x29, #:dtprel_lo12_nc:sym]
ldrsb w23, [x19, #:dtprel_lo12:sym]
ldrsb x17, [x13, :dtprel_lo12_nc:sym]
ldr b11, [x7, #:dtprel_lo12:sym]
// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
ldrb w1, [x2, :tprel_lo12:sym]
ldrsb w3, [x4, #:tprel_lo12_nc:sym]
ldrsb x5, [x6, :tprel_lo12:sym]
ldr b7, [x8, #:tprel_lo12_nc:sym]
// CHECK: ldrb w1, [x2, :tprel_lo12:sym]
// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
ldrh w2, [x3, #:lo12:sym]
ldrsh w5, [x7, :lo12:sym]
ldrsh x11, [x13, #:lo12:sym]
ldr h17, [x19, :lo12:sym]
// CHECK: ldrh w2, [x3, :lo12:sym]
// CHECK: ldrsh w5, [x7, :lo12:sym]
// CHECK: ldrsh x11, [x13, :lo12:sym]
// CHECK: ldr h17, [x19, :lo12:sym]
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
ldrh w23, [x29, #:dtprel_lo12_nc:sym]
ldrsh w23, [x19, :dtprel_lo12:sym]
ldrsh x17, [x13, :dtprel_lo12_nc:sym]
ldr h11, [x7, #:dtprel_lo12:sym]
// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
ldrh w1, [x2, :tprel_lo12:sym]
ldrsh w3, [x4, #:tprel_lo12_nc:sym]
ldrsh x5, [x6, :tprel_lo12:sym]
ldr h7, [x8, #:tprel_lo12_nc:sym]
// CHECK: ldrh w1, [x2, :tprel_lo12:sym]
// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
ldr w1, [x2, #:lo12:sym]
ldrsw x3, [x4, #:lo12:sym]
ldr s4, [x5, :lo12:sym]
// CHECK: ldr w1, [x2, :lo12:sym]
// CHECK: ldrsw x3, [x4, :lo12:sym]
// CHECK: ldr s4, [x5, :lo12:sym]
// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
ldr w1, [x2, :dtprel_lo12:sym]
ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
ldr s4, [x5, #:dtprel_lo12_nc:sym]
// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
ldr w1, [x2, #:tprel_lo12:sym]
ldrsw x3, [x4, :tprel_lo12_nc:sym]
ldr s4, [x5, :tprel_lo12_nc:sym]
// CHECK: ldr w1, [x2, :tprel_lo12:sym]
// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
ldr x28, [x27, :lo12:sym]
ldr d26, [x25, #:lo12:sym]
// CHECK: ldr x28, [x27, :lo12:sym]
// CHECK: ldr d26, [x25, :lo12:sym]
// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
ldr x24, [x23, #:got_lo12:sym]
ldr d22, [x21, :got_lo12:sym]
// CHECK: ldr x24, [x23, :got_lo12:sym]
// CHECK: ldr d22, [x21, :got_lo12:sym]
// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
ldr x24, [x23, :dtprel_lo12_nc:sym]
ldr d22, [x21, #:dtprel_lo12:sym]
// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
ldr x24, [x23, #:tprel_lo12:sym]
ldr d22, [x21, :tprel_lo12_nc:sym]
// CHECK: ldr x24, [x23, :tprel_lo12:sym]
// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
ldr x24, [x23, :gottprel_lo12:sym]
ldr d22, [x21, #:gottprel_lo12:sym]
// CHECK: ldr x24, [x23, :gottprel_lo12:sym]
// CHECK: ldr d22, [x21, :gottprel_lo12:sym]
// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
ldr x24, [x23, #:tlsdesc_lo12:sym]
ldr d22, [x21, :tlsdesc_lo12:sym]
// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
ldr q20, [x19, #:lo12:sym]
// CHECK: ldr q20, [x19, :lo12:sym]
// CHECK-OBJ: R_AARCH64_LDST128_ABS_LO12_NC sym
// Since relocated instructions print without a '#', that syntax should
// certainly be accepted when assembling.
add x3, x5, :lo12:imm
// CHECK: add x3, x5, :lo12:imm
Reference in New Issue View Git Blame Copy Permalink