mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
3d2125c9db
legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
66 lines
1.7 KiB
LLVM
66 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=armv6-apple-darwin -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6
|
|
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF
|
|
|
|
@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
|
|
|
|
declare void @g(i32, i32, i32, i32)
|
|
|
|
define void @t1() {
|
|
; CHECKELF: t1:
|
|
; CHECKELF: bl g(PLT)
|
|
call void @g( i32 1, i32 2, i32 3, i32 4 )
|
|
ret void
|
|
}
|
|
|
|
define void @t2() {
|
|
; CHECKV6: t2:
|
|
; CHECKV6: bx r0 @ TAILCALL
|
|
%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
|
|
%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
|
|
ret void
|
|
}
|
|
|
|
define void @t3() {
|
|
; CHECKV6: t3:
|
|
; CHECKV6: b _t2 @ TAILCALL
|
|
; CHECKELF: t3:
|
|
; CHECKELF: b t2(PLT) @ TAILCALL
|
|
tail call void @t2( ) ; <i32> [#uses=0]
|
|
ret void
|
|
}
|
|
|
|
; Sibcall optimization of expanded libcalls. rdar://8707777
|
|
define double @t4(double %a) nounwind readonly ssp {
|
|
entry:
|
|
; CHECKV6: t4:
|
|
; CHECKV6: b _sin @ TAILCALL
|
|
; CHECKELF: t4:
|
|
; CHECKELF: b sin(PLT) @ TAILCALL
|
|
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
|
|
ret double %0
|
|
}
|
|
|
|
define float @t5(float %a) nounwind readonly ssp {
|
|
entry:
|
|
; CHECKV6: t5:
|
|
; CHECKV6: b _sinf @ TAILCALL
|
|
; CHECKELF: t5:
|
|
; CHECKELF: b sinf(PLT) @ TAILCALL
|
|
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
|
|
ret float %0
|
|
}
|
|
|
|
declare float @sinf(float) nounwind readonly
|
|
|
|
declare double @sin(double) nounwind readonly
|
|
|
|
define i32 @t6(i32 %a, i32 %b) nounwind readnone {
|
|
entry:
|
|
; CHECKV6: t6:
|
|
; CHECKV6: b ___divsi3 @ TAILCALL
|
|
; CHECKELF: t6:
|
|
; CHECKELF: b __aeabi_idiv(PLT) @ TAILCALL
|
|
%0 = sdiv i32 %a, %b
|
|
ret i32 %0
|
|
}
|