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https://github.com/c64scene-ar/llvm-6502.git
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0cfb42adb5
For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 | FileCheck %s
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; ModuleID = 'hh.c'
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
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target triple = "powerpc-apple-darwin9.6"
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; This formerly used R0 for both the stack address and CR.
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define void @foo() nounwind {
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entry:
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;CHECK: mfcr r0
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;CHECK: lis r2, 1
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;CHECK: rlwinm r0, r0, 8, 0, 31
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;CHECK: ori r2, r2, 34540
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;CHECK: stwx r0, r1, r2
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; Make sure that the register scavenger returns the same temporary register.
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;CHECK: lis r2, 1
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;CHECK: mfcr r0
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;CHECK: ori r2, r2, 34536
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;CHECK: rlwinm r0, r0, 12, 0, 31
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;CHECK: stwx r0, r1, r2
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%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
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call void @bar(i8* %x1) nounwind
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call void asm sideeffect "", "~{cr2},~{cr3}"() nounwind
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br label %return
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return: ; preds = %entry
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;CHECK: lis r2, 1
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;CHECK: ori r2, r2, 34540
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;CHECK: lwzx r0, r1, r2
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;CHECK: rlwinm r0, r0, 24, 0, 31
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;CHECK: mtcrf 32, r0
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ret void
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}
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declare void @bar(i8*)
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