mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
d3948116b8
X86/reg-pressure.ll again, and allows us to do nice things in other cases.
For example, we now codegen this sort of thing:
int %loadload(int *%X, int* %Y) {
%Z = load int* %Y
%Y = load int* %X ;; load between %Z and store
%Q = add int %Z, 1
store int %Q, int* %Y
ret int %Y
}
Into this:
loadload:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EAX, DWORD PTR [%EAX]
mov %ECX, DWORD PTR [%ESP + 8]
inc DWORD PTR [%ECX]
ret
where we weren't able to form the 'inc [mem]' before. This also lets the
instruction selector emit loads in any order it wants to, which can be good
for register pressure as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19644 91177308-0d34-0410-b5e6-96231b3b80d8
|
||
|---|---|---|
| .. | ||
| SelectionDAG | ||
| AsmPrinter.cpp | ||
| BranchFolding.cpp | ||
| IntrinsicLowering.cpp | ||
| LiveInterval.cpp | ||
| LiveInterval.h | ||
| LiveIntervalAnalysis.cpp | ||
| LiveIntervalAnalysis.h | ||
| LiveVariables.cpp | ||
| MachineBasicBlock.cpp | ||
| MachineCodeEmitter.cpp | ||
| MachineFunction.cpp | ||
| MachineInstr.cpp | ||
| Makefile | ||
| Passes.cpp | ||
| PHIElimination.cpp | ||
| PhysRegTracker.h | ||
| PrologEpilogInserter.cpp | ||
| RegAllocIterativeScan.cpp | ||
| RegAllocLinearScan.cpp | ||
| RegAllocLocal.cpp | ||
| RegAllocSimple.cpp | ||
| TwoAddressInstructionPass.cpp | ||
| UnreachableBlockElim.cpp | ||
| VirtRegMap.cpp | ||
| VirtRegMap.h | ||