mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-06 05:29:55 +00:00
9de5d0dd42
- Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
233 lines
9.2 KiB
TableGen
233 lines
9.2 KiB
TableGen
//==- IntrinsicsCellSPU.td - Cell SDK intrinsics -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// Department at The Aerospace Corporation and is distributed under the
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Cell SPU Instructions:
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//===----------------------------------------------------------------------===//
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// TODO Items (not urgent today, but would be nice, low priority)
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//
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// ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
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// concatenating the byte argument b as "bbbb". Could recognize this bit pattern
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// in 16-bit and 32-bit constants and reduce instruction count.
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//===----------------------------------------------------------------------===//
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// 7-bit integer type, used as an immediate:
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def cell_i7_ty: LLVMType<i8>;
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def cell_i8_ty: LLVMType<i8>;
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class v16i8_u7imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, cell_i7_ty],
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[IntrNoMem]>;
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class v16i8_u8imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
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[IntrNoMem]>;
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class v16i8_s10imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
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[IntrNoMem]>;
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class v16i8_u16imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
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[IntrNoMem]>;
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class v16i8_rr<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem]>;
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class v8i16_s10imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty],
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[IntrNoMem]>;
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class v8i16_u16imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty],
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[IntrNoMem]>;
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class v8i16_rr<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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class v4i32_rr<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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class v4i32_u7imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, cell_i7_ty],
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[IntrNoMem]>;
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class v4i32_s10imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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class v4i32_u16imm<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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class v4f32_rr<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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class v4f32_rrr<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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class v2f64_rr<string builtin_suffix> :
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GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
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[IntrNoMem]>;
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// All Cell SPU intrinsics start with "llvm.spu.".
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let TargetPrefix = "spu" in {
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def int_spu_si_fsmbi : v8i16_u16imm<"fsmbi">;
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def int_spu_si_ah : v8i16_rr<"ah">;
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def int_spu_si_ahi : v8i16_s10imm<"ahi">;
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def int_spu_si_a : v4i32_rr<"a">;
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def int_spu_si_ai : v4i32_s10imm<"ai">;
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def int_spu_si_sfh : v8i16_rr<"sfh">;
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def int_spu_si_sfhi : v8i16_s10imm<"sfhi">;
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def int_spu_si_sf : v4i32_rr<"sf">;
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def int_spu_si_sfi : v4i32_s10imm<"sfi">;
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def int_spu_si_addx : v4i32_rr<"addx">;
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def int_spu_si_cg : v4i32_rr<"cg">;
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def int_spu_si_cgx : v4i32_rr<"cgx">;
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def int_spu_si_sfx : v4i32_rr<"sfx">;
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def int_spu_si_bg : v4i32_rr<"bg">;
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def int_spu_si_bgx : v4i32_rr<"bgx">;
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def int_spu_si_mpy : // This is special:
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GCCBuiltin<"__builtin_si_mpy">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyu : // This is special:
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GCCBuiltin<"__builtin_si_mpyu">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyi : // This is special:
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GCCBuiltin<"__builtin_si_mpyi">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyui : // This is special:
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GCCBuiltin<"__builtin_si_mpyui">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpya : // This is special:
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GCCBuiltin<"__builtin_si_mpya">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyh : // This is special:
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GCCBuiltin<"__builtin_si_mpyh">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpys : // This is special:
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GCCBuiltin<"__builtin_si_mpys">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyhh : // This is special:
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GCCBuiltin<"__builtin_si_mpyhh">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyhha : // This is special:
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GCCBuiltin<"__builtin_si_mpyhha">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyhhu : // This is special:
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GCCBuiltin<"__builtin_si_mpyhhu">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_mpyhhau : // This is special:
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GCCBuiltin<"__builtin_si_mpyhhau">,
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Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_spu_si_shli: v4i32_u7imm<"shli">;
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def int_spu_si_shlqbi: v16i8_rr<"shlqbi">;
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def int_spu_si_shlqbii: v16i8_u7imm<"shlqbii">;
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def int_spu_si_shlqby: v16i8_rr<"shlqby">;
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def int_spu_si_shlqbyi: v16i8_u7imm<"shlqbyi">;
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def int_spu_si_ceq: v4i32_rr<"ceq">;
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def int_spu_si_ceqi: v4i32_s10imm<"ceqi">;
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def int_spu_si_ceqb: v16i8_rr<"ceqb">;
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def int_spu_si_ceqbi: v16i8_u8imm<"ceqbi">;
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def int_spu_si_ceqh: v8i16_rr<"ceqh">;
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def int_spu_si_ceqhi: v8i16_s10imm<"ceqhi">;
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def int_spu_si_cgt: v4i32_rr<"cgt">;
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def int_spu_si_cgti: v4i32_s10imm<"cgti">;
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def int_spu_si_cgtb: v16i8_rr<"cgtb">;
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def int_spu_si_cgtbi: v16i8_u8imm<"cgtbi">;
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def int_spu_si_cgth: v8i16_rr<"cgth">;
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def int_spu_si_cgthi: v8i16_s10imm<"cgthi">;
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def int_spu_si_clgtb: v16i8_rr<"clgtb">;
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def int_spu_si_clgtbi: v16i8_u8imm<"clgtbi">;
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def int_spu_si_clgth: v8i16_rr<"clgth">;
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def int_spu_si_clgthi: v8i16_s10imm<"clgthi">;
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def int_spu_si_clgt: v4i32_rr<"clgt">;
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def int_spu_si_clgti: v4i32_s10imm<"clgti">;
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def int_spu_si_and: v4i32_rr<"and">;
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def int_spu_si_andbi: v16i8_u8imm<"andbi">;
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def int_spu_si_andc: v4i32_rr<"andc">;
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def int_spu_si_andhi: v8i16_s10imm<"andhi">;
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def int_spu_si_andi: v4i32_s10imm<"andi">;
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def int_spu_si_or: v4i32_rr<"or">;
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def int_spu_si_orbi: v16i8_u8imm<"orbi">;
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def int_spu_si_orc: v4i32_rr<"orc">;
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def int_spu_si_orhi: v8i16_s10imm<"orhi">;
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def int_spu_si_ori: v4i32_s10imm<"ori">;
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def int_spu_si_xor: v4i32_rr<"xor">;
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def int_spu_si_xorbi: v16i8_u8imm<"xorbi">;
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def int_spu_si_xorhi: v8i16_s10imm<"xorhi">;
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def int_spu_si_xori: v4i32_s10imm<"xori">;
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def int_spu_si_nor: v4i32_rr<"nor">;
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def int_spu_si_nand: v4i32_rr<"nand">;
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def int_spu_si_fa: v4f32_rr<"fa">;
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def int_spu_si_fs: v4f32_rr<"fs">;
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def int_spu_si_fm: v4f32_rr<"fm">;
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def int_spu_si_fceq: v4f32_rr<"fceq">;
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def int_spu_si_fcmeq: v4f32_rr<"fcmeq">;
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def int_spu_si_fcgt: v4f32_rr<"fcgt">;
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def int_spu_si_fcmgt: v4f32_rr<"fcmgt">;
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def int_spu_si_fma: v4f32_rrr<"fma">;
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def int_spu_si_fnms: v4f32_rrr<"fnms">;
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def int_spu_si_fms: v4f32_rrr<"fms">;
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def int_spu_si_dfa: v2f64_rr<"dfa">;
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def int_spu_si_dfs: v2f64_rr<"dfs">;
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def int_spu_si_dfm: v2f64_rr<"dfm">;
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//def int_spu_si_dfceq: v2f64_rr<"dfceq">;
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//def int_spu_si_dfcmeq: v2f64_rr<"dfcmeq">;
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//def int_spu_si_dfcgt: v2f64_rr<"dfcgt">;
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//def int_spu_si_dfcmgt: v2f64_rr<"dfcmgt">;
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def int_spu_si_dfnma: v2f64_rr<"dfnma">;
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def int_spu_si_dfma: v2f64_rr<"dfma">;
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def int_spu_si_dfnms: v2f64_rr<"dfnms">;
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def int_spu_si_dfms: v2f64_rr<"dfms">;
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}
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