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https://github.com/c64scene-ar/llvm-6502.git
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8e0f67dcec
Before this patch any program that wanted to know the final symbol name of a GlobalValue had to link with Target. This patch implements a compromise solution where the mangler uses DataLayout. This way, any tool that already links with Target (llc, clang) gets the exact behavior as before and new IR files can be mangled without linking with Target. With this patch the mangler is constructed with just a DataLayout and DataLayout is extended to include the information the Mangler needs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198438 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
4.4 KiB
C++
132 lines
4.4 KiB
C++
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "SparcTargetMachine.h"
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#include "Sparc.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeSparcTarget() {
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// Register the target.
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RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
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RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
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}
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static std::string computeDataLayout(const SparcSubtarget &ST) {
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// Sparc is big endian.
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std::string Ret = "E-m:e";
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// Some ABIs have 32bit pointers.
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if (!ST.is64Bit())
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Ret += "-p:32:32";
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// Alignments for 64 bit integers.
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Ret += "-i64:64";
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// On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
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// On SparcV9 registers can hold 64 or 32 bits, on others only 32.
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if (ST.is64Bit())
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Ret += "-n32:64";
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else
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Ret += "-f128:64-n32";
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if (ST.is64Bit())
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Ret += "-S128";
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else
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Ret += "-S64";
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return Ret;
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}
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/// SparcTargetMachine ctor - Create an ILP32 architecture model
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///
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SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, is64bit),
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DL(computeDataLayout(Subtarget)),
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InstrInfo(Subtarget),
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TLInfo(*this), TSInfo(*this),
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FrameLowering(Subtarget) {
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initAsmInfo();
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}
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namespace {
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/// Sparc Code Generator Pass Configuration Options.
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class SparcPassConfig : public TargetPassConfig {
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public:
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SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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SparcTargetMachine &getSparcTargetMachine() const {
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return getTM<SparcTargetMachine>();
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}
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new SparcPassConfig(this, PM);
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}
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bool SparcPassConfig::addInstSelector() {
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addPass(createSparcISelDag(getSparcTargetMachine()));
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return false;
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}
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bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for Sparc.
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PM.add(createSparcJITCodeEmitterPass(*this, JCE));
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return false;
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}
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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bool SparcPassConfig::addPreEmitPass(){
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addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
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return true;
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}
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void SparcV8TargetMachine::anchor() { }
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SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void SparcV9TargetMachine::anchor() { }
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SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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