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This just adds the basics necessary for allocating the upper words to virtual registers (move, load and store). The move support is parameterised in a way that makes it easy to handle zero extensions, but the associated zero-extend patterns are added by a later patch. The easiest way of testing this seemed to be add a new "h" register constraint for high words. I don't expect the constraint to be useful in real inline asms, but it should work, so I didn't try to hide it behind an option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
168 lines
6.6 KiB
TableGen
168 lines
6.6 KiB
TableGen
//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Class definitions.
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//===----------------------------------------------------------------------===//
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class SystemZReg<string n> : Register<n> {
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let Namespace = "SystemZ";
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}
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class SystemZRegWithSubregs<string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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let Namespace = "SystemZ";
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}
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let Namespace = "SystemZ" in {
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def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
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def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
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def subreg_l64 : SubRegIndex<64, 0>;
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def subreg_h64 : SubRegIndex<64, 64>;
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def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>;
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def subreg_hl32 : ComposedSubRegIndex<subreg_h64, subreg_l32>;
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}
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// Define a register class that contains values of type TYPE and an
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// associated operand called NAME. SIZE is the size and alignment
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// of the registers and REGLIST is the list of individual registers.
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multiclass SystemZRegClass<string name, ValueType type, int size, dag regList> {
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def AsmOperand : AsmOperandClass {
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let Name = name;
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let ParserMethod = "parse"##name;
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let RenderMethod = "addRegOperands";
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}
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def Bit : RegisterClass<"SystemZ", [type], size, regList> {
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let Size = size;
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}
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def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
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let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
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}
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}
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//===----------------------------------------------------------------------===//
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// General-purpose registers
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//===----------------------------------------------------------------------===//
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// Lower 32 bits of one of the 16 64-bit general-purpose registers
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class GPR32<bits<16> num, string n> : SystemZReg<n> {
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let HWEncoding = num;
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}
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// One of the 16 64-bit general-purpose registers.
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class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
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: SystemZRegWithSubregs<n, [low, high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_l32, subreg_h32];
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}
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// 8 even-odd pairs of GPR64s.
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class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
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: SystemZRegWithSubregs<n, [low, high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_l64, subreg_h64];
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}
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// General-purpose registers
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foreach I = 0-15 in {
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def R#I#L : GPR32<I, "r"#I>;
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def R#I#H : GPR32<I, "r"#I>;
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def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
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DwarfRegNum<[I]>;
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}
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foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
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def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
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!cast<GPR64>("R"#I#"D")>;
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}
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/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
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/// together with R14 and R15 in one prolog instruction.
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defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL", 0, 5),
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(sequence "R%uL", 15, 6))>;
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defm GRH32 : SystemZRegClass<"GRH32", i32, 32, (add (sequence "R%uH", 0, 5),
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(sequence "R%uH", 15, 6))>;
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defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5),
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(sequence "R%uD", 15, 6))>;
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// Combine the low and high GR32s into a single class. This can only be
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// used for virtual registers if the high-word facility is available.
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defm GRX32 : SystemZRegClass<"GRX32", i32, 32,
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(add (sequence "R%uL", 0, 5),
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(sequence "R%uH", 0, 5),
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R15L, R15H, R14L, R14H, R13L, R13H,
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R12L, R12H, R11L, R11H, R10L, R10H,
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R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H)>;
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// The architecture doesn't really have any i128 support, so model the
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// register pairs as untyped instead.
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defm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q,
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R12Q, R10Q, R8Q, R6Q,
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R14Q)>;
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// Base and index registers. Everything except R0, which in an address
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// context evaluates as 0.
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defm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0L)>;
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defm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>;
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// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
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// of a GR128.
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defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>;
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//===----------------------------------------------------------------------===//
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// Floating-point registers
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//===----------------------------------------------------------------------===//
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// Lower 32 bits of one of the 16 64-bit floating-point registers
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class FPR32<bits<16> num, string n> : SystemZReg<n> {
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let HWEncoding = num;
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}
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// One of the 16 64-bit floating-point registers
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class FPR64<bits<16> num, string n, FPR32 low>
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: SystemZRegWithSubregs<n, [low]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_h32];
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}
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// 8 pairs of FPR64s, with a one-register gap inbetween.
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class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
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: SystemZRegWithSubregs<n, [low, high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_l64, subreg_h64];
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}
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// Floating-point registers
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foreach I = 0-15 in {
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def F#I#S : FPR32<I, "f"#I>;
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def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
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DwarfRegNum<[!add(I, 16)]>;
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}
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foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {
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def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
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!cast<FPR64>("F"#I#"D")>;
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}
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// There's no store-multiple instruction for FPRs, so we're not fussy
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// about the order in which call-saved registers are allocated.
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defm FP32 : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>;
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defm FP64 : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>;
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defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q,
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F8Q, F9Q, F12Q, F13Q)>;
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//===----------------------------------------------------------------------===//
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// Other registers
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//===----------------------------------------------------------------------===//
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// The 2-bit condition code field of the PSW. Every register named in an
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// inline asm needs a class associated with it.
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def CC : SystemZReg<"cc">;
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def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>;
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