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d410eaba04
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
2.4 KiB
C++
74 lines
2.4 KiB
C++
//=-- Hexagon.h - Top-level interface for Hexagon representation --*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// Hexagon back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_Hexagon_H
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#define TARGET_Hexagon_H
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class FunctionPass;
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class TargetMachine;
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class MachineInstr;
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class MCInst;
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class HexagonAsmPrinter;
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class HexagonTargetMachine;
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class raw_ostream;
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM);
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FunctionPass *createHexagonDelaySlotFillerPass(TargetMachine &TM);
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FunctionPass *createHexagonFPMoverPass(TargetMachine &TM);
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FunctionPass *createHexagonRemoveExtendOps(HexagonTargetMachine &TM);
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FunctionPass *createHexagonCFGOptimizer(HexagonTargetMachine &TM);
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FunctionPass *createHexagonSplitTFRCondSets(HexagonTargetMachine &TM);
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FunctionPass *createHexagonExpandPredSpillCode(HexagonTargetMachine &TM);
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonPeephole();
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FunctionPass *createHexagonFixupHwLoops();
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/* TODO: object output.
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MCCodeEmitter *createHexagonMCCodeEmitter(const Target &,
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TargetMachine &TM,
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MCContext &Ctx);
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*/
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/* TODO: assembler input.
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TargetAsmBackend *createHexagonAsmBackend(const Target &, const std::string &);
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*/
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void HexagonLowerToMC(const MachineInstr *MI, MCInst &MCI,
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HexagonAsmPrinter &AP);
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} // end namespace llvm;
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#define Hexagon_POINTER_SIZE 4
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#define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
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#define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)
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#define Hexagon_WordSize Hexagon_PointerSize
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#define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits
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// allocframe saves LR and FP on stack before allocating
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// a new stack frame. This takes 8 bytes.
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#define HEXAGON_LRFP_SIZE 8
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// Normal instruction size (in bytes).
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#define HEXAGON_INSTR_SIZE 4
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// Maximum number of words in a packet (in instructions).
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#define HEXAGON_PACKET_SIZE 4
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#endif
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