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d410eaba04
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.3 KiB
TableGen
47 lines
1.3 KiB
TableGen
//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V4 instruction classes in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//
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// NV type instructions.
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//
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class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", NV_V4> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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}
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// Definition of Post increment new value store.
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class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<13> imm13;
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}
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// Post increment ST Instruction.
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class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: NVInstPost_V4<outs, ins, asmstr, pattern, cstr> {
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let rt{0-4} = 0;
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}
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class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4> {
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bits<5> rd;
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bits<5> rs;
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bits<6> imm6;
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}
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