mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-10 17:07:06 +00:00
23e70ebf35
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
224 lines
9.9 KiB
TableGen
224 lines
9.9 KiB
TableGen
//===- MBlazeInstrFPU.td - MBlaze FPU Instruction defs -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MBlaze profiles and nodes
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MBlaze Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Memory Access Instructions
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//===----------------------------------------------------------------------===//
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class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
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TA<op, 0x000, (outs FGR32:$dst), (ins memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set FGR32:$dst, (OpNode xaddr:$addr))], IILoad>;
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class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TAI<op, (outs FGR32:$dst), (ins memri:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set FGR32:$dst, (OpNode iaddr:$addr))], IILoad>;
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class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
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TA<op, 0x000, (outs), (ins FGR32:$dst, memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(OpNode FGR32:$dst, xaddr:$addr)], IIStore>;
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class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TAI<op, (outs), (ins FGR32:$dst, memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(OpNode FGR32:$dst, iaddr:$addr)], IIStore>;
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class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
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InstrItinClass itin> :
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TA<op, flags, (outs FGR32:$dst), (ins FGR32:$b, FGR32:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set FGR32:$dst, (OpNode FGR32:$b, FGR32:$c))], itin>;
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class CmpFN<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TA<op, flags, (outs CPURegs:$dst), (ins FGR32:$b, FGR32:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], itin>;
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class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
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InstrItinClass itin> :
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TA<op, flags, (outs FGR32:$dst), (ins FGR32:$b, FGR32:$c),
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!strconcat(instr_asm, " $dst, $c, $b"),
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[(set FGR32:$dst, (OpNode FGR32:$b, FGR32:$c))], itin>;
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class ArithF2<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TF<op, flags, (outs FGR32:$dst), (ins FGR32:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[], itin>;
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class ArithIF<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TF<op, flags, (outs FGR32:$dst), (ins CPURegs:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[], itin>;
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class ArithFI<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TF<op, flags, (outs CPURegs:$dst), (ins FGR32:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[], itin>;
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class LogicF<bits<6> op, string instr_asm> :
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TAI<op, (outs FGR32:$dst), (ins FGR32:$b, FGR32:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[],
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IIAlu>;
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class LogicFI<bits<6> op, string instr_asm> :
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TAI<op, (outs FGR32:$dst), (ins FGR32:$b, fimm:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[],
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IIAlu>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FPU Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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let Predicates=[HasFPU] in {
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def FOR : LogicF<0x28, "or ">;
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def FORI : LogicFI<0x28, "ori ">;
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def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIAlu>;
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def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIAlu>;
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def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>;
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def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>;
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def LWF : LoadFM<0x32, "lw ", load>;
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def LWFI : LoadFMI<0x32, "lwi ", load>;
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def SWF : StoreFM<0x32, "sw ", store>;
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def SWFI : StoreFMI<0x32, "swi ", store>;
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}
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let Predicates=[HasFPU,HasSqrt] in {
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def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>;
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def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>;
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def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>;
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}
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let isAsCheapAsAMove = 1 in {
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def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIAlu>;
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def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIAlu>;
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def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIAlu>;
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def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIAlu>;
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def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIAlu>;
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def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIAlu>;
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def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIAlu>;
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}
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let usesCustomInserter = 1 in {
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def Select_FCC : MBlazePseudo<(outs FGR32:$dst),
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(ins FGR32:$T, FGR32:$F, CPURegs:$CMP, i32imm:$CC),
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"; SELECT_FCC PSEUDO!",
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[]>;
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}
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// Floating point conversions
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let Predicates=[HasFPU] in {
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def : Pat<(sint_to_fp CPURegs:$V), (FLT CPURegs:$V)>;
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def : Pat<(fp_to_sint FGR32:$V), (FINT FGR32:$V)>;
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def : Pat<(fsqrt FGR32:$V), (FSQRT FGR32:$V)>;
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}
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// SET_CC operations
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let Predicates=[HasFPU] in {
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETEQ),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_EQ FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETNE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_EQ FGR32:$L, FGR32:$R), 1)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETOEQ),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_EQ FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETONE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(XOR (FCMP_UN FGR32:$L, FGR32:$R),
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(FCMP_EQ FGR32:$L, FGR32:$R)), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETONE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(OR (FCMP_UN FGR32:$L, FGR32:$R),
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(FCMP_EQ FGR32:$L, FGR32:$R)), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETGT),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_GT FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETLT),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_LT FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETGE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_GE FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETLE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_LE FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETOGT),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_GT FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETOLT),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_LT FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETOGE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_GE FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETOLE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_LE FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETUEQ),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(OR (FCMP_UN FGR32:$L, FGR32:$R),
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(FCMP_EQ FGR32:$L, FGR32:$R)), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETUNE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_NE FGR32:$L, FGR32:$R), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETUGT),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(OR (FCMP_UN FGR32:$L, FGR32:$R),
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(FCMP_GT FGR32:$L, FGR32:$R)), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETULT),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(OR (FCMP_UN FGR32:$L, FGR32:$R),
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(FCMP_LT FGR32:$L, FGR32:$R)), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETUGE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(OR (FCMP_UN FGR32:$L, FGR32:$R),
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(FCMP_GE FGR32:$L, FGR32:$R)), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETULE),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(OR (FCMP_UN FGR32:$L, FGR32:$R),
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(FCMP_LE FGR32:$L, FGR32:$R)), 2)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETO),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_UN FGR32:$L, FGR32:$R), 1)>;
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def : Pat<(setcc FGR32:$L, FGR32:$R, SETUO),
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(Select_CC (ADDI R0, 1), (ADDI R0, 0),
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(FCMP_UN FGR32:$L, FGR32:$R), 2)>;
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}
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// SELECT operations
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def : Pat<(select CPURegs:$C, FGR32:$T, FGR32:$F),
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(Select_FCC FGR32:$T, FGR32:$F, CPURegs:$C, 2)>;
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//===----------------------------------------------------------------------===//
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// Patterns for Floating Point Instructions
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//===----------------------------------------------------------------------===//
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def : Pat<(f32 fpimm:$imm), (FORI F0, fpimm:$imm)>;
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