mirror of
https://github.com/c64scene-ar/llvm-6502.git
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9e08876a2a
instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
1.7 KiB
LLVM
77 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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define i32 @f1(i32 %a, i32* %v) {
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; CHECK: f1:
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; CHECK: str r0, [r1]
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store i32 %a, i32* %v
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ret i32 %a
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}
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define i32 @f2(i32 %a, i32* %v) {
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; CHECK: f2:
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; CHECK: str.w r0, [r1, #4092]
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%tmp2 = getelementptr i32* %v, i32 1023
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store i32 %a, i32* %tmp2
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ret i32 %a
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}
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define i32 @f2a(i32 %a, i32* %v) {
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; CHECK: f2a:
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; CHECK: str r0, [r1, #-128]
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%tmp2 = getelementptr i32* %v, i32 -32
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store i32 %a, i32* %tmp2
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ret i32 %a
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}
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define i32 @f3(i32 %a, i32* %v) {
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; CHECK: f3:
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; CHECK: mov.w r2, #4096
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; CHECK: str r0, [r1, r2]
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%tmp2 = getelementptr i32* %v, i32 1024
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store i32 %a, i32* %tmp2
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ret i32 %a
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}
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define i32 @f4(i32 %a, i32 %base) {
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entry:
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; CHECK: f4:
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; CHECK: str r0, [r1, #-128]
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%tmp1 = sub i32 %base, 128
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%tmp2 = inttoptr i32 %tmp1 to i32*
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store i32 %a, i32* %tmp2
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ret i32 %a
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}
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define i32 @f5(i32 %a, i32 %base, i32 %offset) {
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entry:
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; CHECK: f5:
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; CHECK: str r0, [r1, r2]
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%tmp1 = add i32 %base, %offset
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%tmp2 = inttoptr i32 %tmp1 to i32*
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store i32 %a, i32* %tmp2
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ret i32 %a
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}
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define i32 @f6(i32 %a, i32 %base, i32 %offset) {
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entry:
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; CHECK: f6:
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; CHECK: str.w r0, [r1, r2, lsl #2]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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store i32 %a, i32* %tmp3
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ret i32 %a
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}
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define i32 @f7(i32 %a, i32 %base, i32 %offset) {
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entry:
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; CHECK: f7:
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; CHECK: lsrs r2, r2, #2
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; CHECK: str r0, [r1, r2]
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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store i32 %a, i32* %tmp3
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ret i32 %a
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}
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