mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
4.8 KiB
LLVM
88 lines
4.8 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -verify-machineinstrs
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -verify-machineinstrs -O0
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
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target triple = "thumbv7-apple-darwin10"
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; This function would crash LiveIntervalAnalysis by creating a chain of 4 INSERT_SUBREGs of the same register.
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define arm_apcscc void @NEON_vst4q_u32(i32* nocapture %sp0, i32* nocapture %sp1, i32* nocapture %sp2, i32* nocapture %sp3, i32* %dp) nounwind {
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entry:
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%0 = bitcast i32* %sp0 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
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%1 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
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%2 = bitcast i32* %sp1 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
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%3 = load <4 x i32>, <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1]
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%4 = bitcast i32* %sp2 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
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%5 = load <4 x i32>, <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1]
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%6 = bitcast i32* %sp3 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
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%7 = load <4 x i32>, <4 x i32>* %6, align 16 ; <<4 x i32>> [#uses=1]
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%8 = bitcast i32* %dp to i8* ; <i8*> [#uses=1]
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tail call void @llvm.arm.neon.vst4.v4i32(i8* %8, <4 x i32> %1, <4 x i32> %3, <4 x i32> %5, <4 x i32> %7, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
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@sbuf = common global [16 x i32] zeroinitializer, align 16 ; <[16 x i32]*> [#uses=5]
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@dbuf = common global [16 x i32] zeroinitializer ; <[16 x i32]*> [#uses=2]
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; This function creates 4 chained INSERT_SUBREGS and then invokes the register scavenger.
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; The first INSERT_SUBREG needs an <undef> use operand for that to work.
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define arm_apcscc i32 @main() nounwind {
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bb.nph:
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br label %bb
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bb: ; preds = %bb, %bb.nph
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%0 = phi i32 [ 0, %bb.nph ], [ %1, %bb ] ; <i32> [#uses=4]
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%scevgep = getelementptr [16 x i32], [16 x i32]* @sbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
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%scevgep5 = getelementptr [16 x i32], [16 x i32]* @dbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
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store i32 %0, i32* %scevgep, align 4
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store i32 -1, i32* %scevgep5, align 4
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%1 = add nsw i32 %0, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %1, 16 ; <i1> [#uses=1]
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br i1 %exitcond, label %bb2, label %bb
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bb2: ; preds = %bb
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%2 = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @sbuf to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
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%3 = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 4) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
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%4 = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 8) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
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%5 = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 12) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
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tail call void @llvm.arm.neon.vst4.v4i32(i8* bitcast ([16 x i32]* @dbuf to i8*), <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5, i32 1) nounwind
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ret i32 0
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}
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; PR12389
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; Make sure the DPair register class can spill.
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define void @pr12389(i8* %p) nounwind ssp {
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entry:
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%vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %p, i32 1)
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tail call void asm sideeffect "", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15}"() nounwind
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tail call void @llvm.arm.neon.vst1.v4f32(i8* %p, <4 x float> %vld1, i32 1)
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ret void
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}
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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; <rdar://problem/11101911>
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; When an strd is expanded into two str instructions, make sure the first str
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; doesn't kill the base register. This can happen if the base register is the
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; same as the data register.
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%class = type { i8*, %class*, i32 }
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define void @f11101911(%class* %this, i32 %num) ssp align 2 {
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entry:
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%p1 = getelementptr inbounds %class, %class* %this, i32 0, i32 1
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%p2 = getelementptr inbounds %class, %class* %this, i32 0, i32 2
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tail call void asm sideeffect "", "~{r1},~{r3},~{r5},~{r11},~{r13}"() nounwind
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store %class* %this, %class** %p1, align 4
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store i32 %num, i32* %p2, align 4
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ret void
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}
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; Check RAFast handling of inline assembly with many dense clobbers.
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; The large tuple aliases of the vector registers can cause problems.
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define void @rdar13249625(double* nocapture %p) nounwind {
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%1 = tail call double asm sideeffect "@ $0", "=w,~{d0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15}"() nounwind
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store double %1, double* %p, align 4
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ret void
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}
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