Simon Pilgrim 44226ffc19 [X86][SSE] Vectorized i8 and i16 shift operators ... This patch ensures that SHL/SRL/SRA shifts for i8 and i16 vectors avoid scalarization. It builds on the existing i8 SHL vectorized implementation of moving the shift bits up to the sign bit position and separating the 4, 2 & 1 bit shifts with several improvements: 1 - SSE41 targets can use (v)pblendvb directly with the sign bit instead of performing a comparison to feed into a VSELECT node. 2 - pre-SSE41 targets were masking + comparing with an 0x80 constant - we avoid this by using the fact that a set sign bit means a negative integer which can be compared against zero to then feed into VSELECT, avoiding the need for a constant mask (zero generation is much cheaper). 3 - SRA i8 needs to be unpacked to the upper byte of a i16 so that the i16 psraw instruction can be correctly used for sign extension - we have to do more work than for SHL/SRL but perf tests indicate that this is still beneficial. The i16 implementation is similar but simpler than for i8 - we have to do 8, 4, 2 & 1 bit shifts but less shift masking is involved. SSE41 use of (v)pblendvb requires that the i16 shift amount is splatted to both bytes however. Tested on SSE2, SSE41 and AVX machines. Differential Revision: http://reviews.llvm.org/D9474 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239509 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-11 07:46:37 +00:00
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AArch64	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
ARM	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
PowerPC	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
X86	[X86][SSE] Vectorized i8 and i16 shift operators	2015-06-11 07:46:37 +00:00
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