mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
07efe87198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213586 91177308-0d34-0410-b5e6-96231b3b80d8
183 lines
4.5 KiB
LLVM
183 lines
4.5 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; CHECK-LABEL: atom0
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define i32 @atom0(i32* %addr, i32 %val) {
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; CHECK: atom.add.u32
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%ret = atomicrmw add i32* %addr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom1
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define i64 @atom1(i64* %addr, i64 %val) {
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; CHECK: atom.add.u64
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%ret = atomicrmw add i64* %addr, i64 %val seq_cst
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ret i64 %ret
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}
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; CHECK-LABEL: atom2
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define i32 @atom2(i32* %subr, i32 %val) {
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; CHECK: neg.s32
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; CHECK: atom.add.u32
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%ret = atomicrmw sub i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom3
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define i64 @atom3(i64* %subr, i64 %val) {
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; CHECK: neg.s64
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; CHECK: atom.add.u64
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%ret = atomicrmw sub i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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; CHECK-LABEL: atom4
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define i32 @atom4(i32* %subr, i32 %val) {
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; CHECK: atom.and.b32
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%ret = atomicrmw and i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom5
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define i64 @atom5(i64* %subr, i64 %val) {
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; CHECK: atom.and.b64
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%ret = atomicrmw and i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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;; NAND not yet supported
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;define i32 @atom6(i32* %subr, i32 %val) {
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; %ret = atomicrmw nand i32* %subr, i32 %val seq_cst
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; ret i32 %ret
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;}
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;define i64 @atom7(i64* %subr, i64 %val) {
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; %ret = atomicrmw nand i64* %subr, i64 %val seq_cst
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; ret i64 %ret
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;}
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; CHECK-LABEL: atom8
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define i32 @atom8(i32* %subr, i32 %val) {
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; CHECK: atom.or.b32
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%ret = atomicrmw or i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom9
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define i64 @atom9(i64* %subr, i64 %val) {
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; CHECK: atom.or.b64
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%ret = atomicrmw or i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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; CHECK-LABEL: atom10
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define i32 @atom10(i32* %subr, i32 %val) {
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; CHECK: atom.xor.b32
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%ret = atomicrmw xor i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom11
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define i64 @atom11(i64* %subr, i64 %val) {
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; CHECK: atom.xor.b64
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%ret = atomicrmw xor i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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; CHECK-LABEL: atom12
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define i32 @atom12(i32* %subr, i32 %val) {
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; CHECK: atom.max.s32
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%ret = atomicrmw max i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom13
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define i64 @atom13(i64* %subr, i64 %val) {
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; CHECK: atom.max.s64
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%ret = atomicrmw max i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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; CHECK-LABEL: atom14
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define i32 @atom14(i32* %subr, i32 %val) {
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; CHECK: atom.min.s32
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%ret = atomicrmw min i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom15
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define i64 @atom15(i64* %subr, i64 %val) {
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; CHECK: atom.min.s64
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%ret = atomicrmw min i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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; CHECK-LABEL: atom16
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define i32 @atom16(i32* %subr, i32 %val) {
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; CHECK: atom.max.u32
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%ret = atomicrmw umax i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom17
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define i64 @atom17(i64* %subr, i64 %val) {
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; CHECK: atom.max.u64
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%ret = atomicrmw umax i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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; CHECK-LABEL: atom18
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define i32 @atom18(i32* %subr, i32 %val) {
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; CHECK: atom.min.u32
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%ret = atomicrmw umin i32* %subr, i32 %val seq_cst
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ret i32 %ret
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}
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; CHECK-LABEL: atom19
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define i64 @atom19(i64* %subr, i64 %val) {
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; CHECK: atom.min.u64
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%ret = atomicrmw umin i64* %subr, i64 %val seq_cst
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ret i64 %ret
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}
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declare float @llvm.nvvm.atomic.load.add.f32.p0f32(float* %addr, float %val)
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; CHECK-LABEL: atomic_add_f32_generic
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define float @atomic_add_f32_generic(float* %addr, float %val) {
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; CHECK: atom.add.f32
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%ret = call float @llvm.nvvm.atomic.load.add.f32.p0f32(float* %addr, float %val)
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ret float %ret
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}
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declare float @llvm.nvvm.atomic.load.add.f32.p1f32(float addrspace(1)* %addr, float %val)
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; CHECK-LABEL: atomic_add_f32_addrspace1
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define float @atomic_add_f32_addrspace1(float addrspace(1)* %addr, float %val) {
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; CHECK: atom.global.add.f32
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%ret = call float @llvm.nvvm.atomic.load.add.f32.p1f32(float addrspace(1)* %addr, float %val)
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ret float %ret
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}
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declare float @llvm.nvvm.atomic.load.add.f32.p3f32(float addrspace(3)* %addr, float %val)
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; CHECK-LABEL: atomic_add_f32_addrspace3
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define float @atomic_add_f32_addrspace3(float addrspace(3)* %addr, float %val) {
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; CHECK: atom.shared.add.f32
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%ret = call float @llvm.nvvm.atomic.load.add.f32.p3f32(float addrspace(3)* %addr, float %val)
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ret float %ret
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}
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; CHECK-LABEL: atomic_cmpxchg_i32
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define i32 @atomic_cmpxchg_i32(i32* %addr, i32 %cmp, i32 %new) {
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; CHECK: atom.cas.b32
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%pairold = cmpxchg i32* %addr, i32 %cmp, i32 %new seq_cst seq_cst
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ret i32 %new
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}
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; CHECK-LABEL: atomic_cmpxchg_i64
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define i64 @atomic_cmpxchg_i64(i64* %addr, i64 %cmp, i64 %new) {
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; CHECK: atom.cas.b64
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%pairold = cmpxchg i64* %addr, i64 %cmp, i64 %new seq_cst seq_cst
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ret i64 %new
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}
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