Owen Anderson d451f888b8 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower ...

half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8

2010-10-21 20:21:49 +00:00

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Analysis

Explain what "constant" means here.

2010-10-21 19:45:09 +00:00

Archive

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AsmParser

AlignLoc is never used for anything - zap it (gcc-4.6 warning).

2010-10-21 16:07:10 +00:00

Bitcode

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CodeGen

Don't include the destination interval in the union when computing

2010-10-21 18:47:08 +00:00

CompilerDriver

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ExecutionEngine

Fix the cleanup process of exception information in JIT. Now JIT

2010-10-21 08:57:29 +00:00

Linker

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MC

Do not recurse into symbol refs that have a variant kind. This prevents us

2010-10-21 18:00:20 +00:00

Support

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System

Use C++03...

2010-10-20 16:00:45 +00:00

Target

ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower

2010-10-21 20:21:49 +00:00

Transforms

RetOp is not actually used for anything useful (though

2010-10-21 16:05:44 +00:00

VMCore

Attempt to fix valgrind complaining about (benign) leaks in pass registration by having PassRegistry

2010-10-20 22:22:30 +00:00

Makefile

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